1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * include/configs/lager.h 4 * This file is lager board configuration. 5 * 6 * Copyright (C) 2013, 2014 Renesas Electronics Corporation 7 */ 8 9#ifndef __LAGER_H 10#define __LAGER_H 11 12#include "rcar-gen2-common.h" 13 14#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 15#define STACK_AREA_SIZE 0x00100000 16#define LOW_LEVEL_MERAM_STACK \ 17 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 18 19/* MEMORY */ 20#define RCAR_GEN2_SDRAM_BASE 0x40000000 21#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) 22#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 23 24/* SH Ether */ 25#define CONFIG_SH_ETHER_USE_PORT 0 26#define CONFIG_SH_ETHER_PHY_ADDR 0x1 27#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 28#define CONFIG_SH_ETHER_CACHE_WRITEBACK 29#define CONFIG_SH_ETHER_CACHE_INVALIDATE 30#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 31#define CONFIG_BITBANGMII 32#define CONFIG_BITBANGMII_MULTI 33 34/* Board Clock */ 35#define RMOBILE_XTAL_CLK 20000000u 36#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 37 38#define CONFIG_EXTRA_ENV_SETTINGS \ 39 "bootm_size=0x10000000\0" 40 41/* SPL support */ 42#define CONFIG_SPL_STACK 0xe6340000 43#define CONFIG_SPL_MAX_SIZE 0x4000 44#ifdef CONFIG_SPL_BUILD 45#define CONFIG_CONS_SCIF0 46#define CONFIG_SH_SCIF_CLK_FREQ 65000000 47#endif 48 49#endif /* __LAGER_H */ 50