1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6#ifndef __CONFIG_H 7#define __CONFIG_H 8 9#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 10 11#define CONFIG_SYS_FSL_CLK 12 13/* 14 * Size of malloc() pool 15 */ 16#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 17 18#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 19#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 20 21#define CONFIG_SYS_CLK_FREQ 100000000 22#define CONFIG_DDR_CLK_FREQ 100000000 23 24/* 25 * DDR: 800 MHz ( 1600 MT/s data rate ) 26 */ 27 28#define DDR_SDRAM_CFG 0x470c0008 29#define DDR_CS0_BNDS 0x008000bf 30#define DDR_CS0_CONFIG 0x80014302 31#define DDR_TIMING_CFG_0 0x50550004 32#define DDR_TIMING_CFG_1 0xbcb38c56 33#define DDR_TIMING_CFG_2 0x0040d120 34#define DDR_TIMING_CFG_3 0x010e1000 35#define DDR_TIMING_CFG_4 0x00000001 36#define DDR_TIMING_CFG_5 0x03401400 37#define DDR_SDRAM_CFG_2 0x00401010 38#define DDR_SDRAM_MODE 0x00061c60 39#define DDR_SDRAM_MODE_2 0x00180000 40#define DDR_SDRAM_INTERVAL 0x18600618 41#define DDR_DDR_WRLVL_CNTL 0x8655f605 42#define DDR_DDR_WRLVL_CNTL_2 0x05060607 43#define DDR_DDR_WRLVL_CNTL_3 0x05050505 44#define DDR_DDR_CDR1 0x80040000 45#define DDR_DDR_CDR2 0x00000001 46#define DDR_SDRAM_CLK_CNTL 0x02000000 47#define DDR_DDR_ZQ_CNTL 0x89080600 48#define DDR_CS0_CONFIG_2 0 49#define DDR_SDRAM_CFG_MEM_EN 0x80000000 50#define SDRAM_CFG2_D_INIT 0x00000010 51#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 52#define SDRAM_CFG2_FRC_SR 0x80000000 53#define SDRAM_CFG_BI 0x00000001 54 55#ifdef CONFIG_RAMBOOT_PBL 56#define CONFIG_SYS_FSL_PBL_PBI \ 57 board/freescale/ls1021aiot/ls102xa_pbi.cfg 58#endif 59 60#ifdef CONFIG_SD_BOOT 61#define CONFIG_SYS_FSL_PBL_RCW \ 62 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg 63#define CONFIG_SPL_LIBCOMMON_SUPPORT 64#define CONFIG_SPL_LIBGENERIC_SUPPORT 65#define CONFIG_SPL_ENV_SUPPORT 66#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 67#define CONFIG_SPL_I2C_SUPPORT 68#define CONFIG_SPL_WATCHDOG_SUPPORT 69#define CONFIG_SPL_MMC_SUPPORT 70#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 71 72#define CONFIG_SPL_MAX_SIZE 0x1a000 73#define CONFIG_SPL_STACK 0x1001d000 74#define CONFIG_SPL_PAD_TO 0x1c000 75 76#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 77 CONFIG_SYS_MONITOR_LEN) 78#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 79#define CONFIG_SPL_BSS_START_ADDR 0x80100000 80#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 81#define CONFIG_SYS_MONITOR_LEN 0x80000 82#endif 83 84#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 85#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 86 87#define CONFIG_CHIP_SELECTS_PER_CTRL 4 88 89/* 90 * Serial Port 91 */ 92#define CONFIG_SYS_NS16550_SERIAL 93#define CONFIG_SYS_NS16550_REG_SIZE 1 94#define CONFIG_SYS_NS16550_CLK get_serial_clock() 95 96/* 97 * I2C 98 */ 99#define CONFIG_CMD_I2C 100#define CONFIG_SYS_I2C 101#define CONFIG_SYS_I2C_MXC 102#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 103#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 104#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 105 106/* EEPROM */ 107#define CONFIG_ID_EEPROM 108#define CONFIG_SYS_I2C_EEPROM_NXID 109#define CONFIG_SYS_EEPROM_BUS_NUM 0 110#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 111#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 112 113/* 114 * MMC 115 */ 116#define CONFIG_CMD_MMC 117 118/* SATA */ 119#define CONFIG_SCSI_AHCI_PLAT 120#ifndef PCI_DEVICE_ID_FREESCALE_AHCI 121#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 122#endif 123#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 124 PCI_DEVICE_ID_FREESCALE_AHCI} 125 126#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 127#define CONFIG_SYS_SCSI_MAX_LUN 1 128#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 129 CONFIG_SYS_SCSI_MAX_LUN) 130 131/* SPI */ 132#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 133#define CONFIG_SPI_FLASH_SPANSION 134 135/* QSPI */ 136#define QSPI0_AMBA_BASE 0x40000000 137#define FSL_QSPI_FLASH_SIZE (1 << 24) 138#define FSL_QSPI_FLASH_NUM 2 139#define CONFIG_SPI_FLASH_SPANSION 140#endif 141 142/* DM SPI */ 143#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 144#define CONFIG_CMD_SF 145#define CONFIG_DM_SPI_FLASH 146#endif 147 148/* 149 * eTSEC 150 */ 151 152#ifdef CONFIG_TSEC_ENET 153#define CONFIG_MII_DEFAULT_TSEC 1 154#define CONFIG_TSEC1 1 155#define CONFIG_TSEC1_NAME "eTSEC1" 156#define CONFIG_TSEC2 1 157#define CONFIG_TSEC2_NAME "eTSEC2" 158 159#define TSEC1_PHY_ADDR 1 160#define TSEC2_PHY_ADDR 3 161 162#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 163#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 164 165#define TSEC1_PHYIDX 0 166#define TSEC2_PHYIDX 0 167 168#define CONFIG_ETHPRIME "eTSEC2" 169 170#define CONFIG_PHY_ATHEROS 171 172#define CONFIG_HAS_ETH0 173#define CONFIG_HAS_ETH1 174#define CONFIG_HAS_ETH2 175#endif 176 177/* PCIe */ 178#define CONFIG_PCIE1 /* PCIE controler 1 */ 179#define CONFIG_PCIE2 /* PCIE controler 2 */ 180 181#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 182 183#ifdef CONFIG_PCI 184#define CONFIG_PCI_SCAN_SHOW 185#endif 186 187#define CONFIG_CMD_MII 188 189#define CONFIG_CMDLINE_TAG 190 191#define CONFIG_PEN_ADDR_BIG_ENDIAN 192#define CONFIG_LAYERSCAPE_NS_ACCESS 193#define CONFIG_SMP_PEN_ADDR 0x01ee0200 194#define COUNTER_FREQUENCY 12500000 195 196#define CONFIG_HWCONFIG 197#define HWCONFIG_BUFFER_SIZE 256 198 199#define CONFIG_FSL_DEVICE_DISABLE 200 201#define CONFIG_EXTRA_ENV_SETTINGS \ 202 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 203"initrd_high=0xffffffff\0" \ 204"fdt_high=0xffffffff\0" 205 206/* 207 * Miscellaneous configurable options 208 */ 209#define CONFIG_CMD_GREPENV 210#define CONFIG_CMD_MEMINFO 211 212#define CONFIG_SYS_LOAD_ADDR 0x82000000 213 214#define CONFIG_LS102XA_STREAM_ID 215 216#define CONFIG_SYS_INIT_SP_OFFSET \ 217 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 218#define CONFIG_SYS_INIT_SP_ADDR \ 219 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 220 221#ifdef CONFIG_SPL_BUILD 222#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 223#else 224/* start of monitor */ 225#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 226#endif 227 228#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 229 230/* 231 * Environment 232 */ 233 234#define CONFIG_ENV_OVERWRITE 235 236#if defined(CONFIG_SD_BOOT) 237#define CONFIG_SYS_MMC_ENV_DEV 0 238#endif 239 240#define CONFIG_OF_BOARD_SETUP 241#define CONFIG_OF_STDOUT_VIA_ALIAS 242 243#include <asm/fsl_secure_boot.h> 244 245#endif 246