1
2
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4
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
9#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
10
11#define CONFIG_SYS_FSL_CLK
12
13#define CONFIG_DEEP_SLEEP
14
15
16#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
17
18#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
19#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
20
21
22#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
23
24#define CONFIG_SYS_CLK_FREQ 100000000
25#define CONFIG_DDR_CLK_FREQ 100000000
26
27#define DDR_SDRAM_CFG 0x470c0008
28#define DDR_CS0_BNDS 0x008000bf
29#define DDR_CS0_CONFIG 0x80014302
30#define DDR_TIMING_CFG_0 0x50550004
31#define DDR_TIMING_CFG_1 0xbcb38c56
32#define DDR_TIMING_CFG_2 0x0040d120
33#define DDR_TIMING_CFG_3 0x010e1000
34#define DDR_TIMING_CFG_4 0x00000001
35#define DDR_TIMING_CFG_5 0x03401400
36#define DDR_SDRAM_CFG_2 0x00401010
37#define DDR_SDRAM_MODE 0x00061c60
38#define DDR_SDRAM_MODE_2 0x00180000
39#define DDR_SDRAM_INTERVAL 0x18600618
40#define DDR_DDR_WRLVL_CNTL 0x8655f605
41#define DDR_DDR_WRLVL_CNTL_2 0x05060607
42#define DDR_DDR_WRLVL_CNTL_3 0x05050505
43#define DDR_DDR_CDR1 0x80040000
44#define DDR_DDR_CDR2 0x00000001
45#define DDR_SDRAM_CLK_CNTL 0x02000000
46#define DDR_DDR_ZQ_CNTL 0x89080600
47#define DDR_CS0_CONFIG_2 0
48#define DDR_SDRAM_CFG_MEM_EN 0x80000000
49#define SDRAM_CFG2_D_INIT 0x00000010
50#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
51#define SDRAM_CFG2_FRC_SR 0x80000000
52#define SDRAM_CFG_BI 0x00000001
53
54#ifdef CONFIG_RAMBOOT_PBL
55#define CONFIG_SYS_FSL_PBL_PBI \
56 "board/freescale/ls1021atsn/ls102xa_pbi.cfg"
57#endif
58
59#ifdef CONFIG_SD_BOOT
60#define CONFIG_SYS_FSL_PBL_RCW \
61 "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
62
63#ifdef CONFIG_SECURE_BOOT
64#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
65#endif
66
67#define CONFIG_SPL_MAX_SIZE 0x1a000
68#define CONFIG_SPL_STACK 0x1001d000
69#define CONFIG_SPL_PAD_TO 0x1c000
70
71#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
72 CONFIG_SYS_MONITOR_LEN)
73#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
74#define CONFIG_SPL_BSS_START_ADDR 0x80100000
75#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
76
77#ifdef CONFIG_U_BOOT_HDR_SIZE
78
79
80
81
82
83
84#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
85#else
86#define CONFIG_SYS_MONITOR_LEN 0x100000
87#endif
88#endif
89
90#define CONFIG_NR_DRAM_BANKS 1
91#define PHYS_SDRAM 0x80000000
92#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
93
94#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
95#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
96
97#define CONFIG_CHIP_SELECTS_PER_CTRL 4
98
99
100#define CONFIG_CONS_INDEX 1
101#define CONFIG_SYS_NS16550_SERIAL
102#ifndef CONFIG_DM_SERIAL
103#define CONFIG_SYS_NS16550_REG_SIZE 1
104#endif
105#define CONFIG_SYS_NS16550_CLK get_serial_clock()
106
107#define CONFIG_BAUDRATE 115200
108
109
110#define CONFIG_SYS_I2C
111#define CONFIG_SYS_I2C_MXC
112#define CONFIG_SYS_I2C_MXC_I2C1
113#define CONFIG_SYS_I2C_MXC_I2C2
114#define CONFIG_SYS_I2C_MXC_I2C3
115
116
117#define CONFIG_ID_EEPROM
118#define CONFIG_SYS_I2C_EEPROM_NXID
119#define CONFIG_SYS_EEPROM_BUS_NUM 0
120#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
121#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
122
123
124#define FSL_QSPI_FLASH_SIZE (1 << 24)
125#define FSL_QSPI_FLASH_NUM 2
126
127
128#define CONFIG_PCIE1
129#define CONFIG_PCIE2
130#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
131#ifdef CONFIG_PCI
132#define CONFIG_PCI_SCAN_SHOW
133#endif
134
135#define CONFIG_LAYERSCAPE_NS_ACCESS
136#define COUNTER_FREQUENCY 12500000
137
138#define CONFIG_HWCONFIG
139#define HWCONFIG_BUFFER_SIZE 256
140
141#define CONFIG_FSL_DEVICE_DISABLE
142
143#define BOOT_TARGET_DEVICES(func) \
144 func(MMC, mmc, 0) \
145 func(USB, usb, 0) \
146 func(DHCP, dhcp, na)
147#include <config_distro_bootcmd.h>
148
149#define CONFIG_EXTRA_ENV_SETTINGS \
150 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
151 "initrd_high=0xffffffff\0" \
152 "fdt_high=0xffffffff\0" \
153 "fdt_addr=0x64f00000\0" \
154 "kernel_addr=0x61000000\0" \
155 "kernelheader_addr=0x60800000\0" \
156 "scriptaddr=0x80000000\0" \
157 "scripthdraddr=0x80080000\0" \
158 "fdtheader_addr_r=0x80100000\0" \
159 "kernelheader_addr_r=0x80200000\0" \
160 "kernel_addr_r=0x80008000\0" \
161 "kernelheader_size=0x40000\0" \
162 "fdt_addr_r=0x8f000000\0" \
163 "ramdisk_addr_r=0xa0000000\0" \
164 "load_addr=0x80008000\0" \
165 "kernel_size=0x2800000\0" \
166 "kernel_addr_sd=0x8000\0" \
167 "kernel_size_sd=0x14000\0" \
168 "kernelhdr_addr_sd=0x4000\0" \
169 "kernelhdr_size_sd=0x10\0" \
170 BOOTENV \
171 "boot_scripts=ls1021atsn_boot.scr\0" \
172 "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
173 "scan_dev_for_boot_part=" \
174 "part list ${devtype} ${devnum} devplist; " \
175 "env exists devplist || setenv devplist 1; " \
176 "for distro_bootpart in ${devplist}; do " \
177 "if fstype ${devtype} " \
178 "${devnum}:${distro_bootpart} " \
179 "bootfstype; then " \
180 "run scan_dev_for_boot; " \
181 "fi; " \
182 "done\0" \
183 "scan_dev_for_boot=" \
184 "echo Scanning ${devtype} " \
185 "${devnum}:${distro_bootpart}...; " \
186 "for prefix in ${boot_prefixes}; do " \
187 "run scan_dev_for_scripts; " \
188 "run scan_dev_for_extlinux; " \
189 "done;" \
190 "\0" \
191 "boot_a_script=" \
192 "load ${devtype} ${devnum}:${distro_bootpart} " \
193 "${scriptaddr} ${prefix}${script}; " \
194 "env exists secureboot && load ${devtype} " \
195 "${devnum}:${distro_bootpart} " \
196 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
197 "&& esbc_validate ${scripthdraddr};" \
198 "source ${scriptaddr}\0" \
199 "qspi_bootcmd=echo Trying load from qspi..;" \
200 "sf probe && sf read $load_addr " \
201 "$kernel_addr $kernel_size; env exists secureboot " \
202 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
203 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
204 "bootm $load_addr#$board\0" \
205 "sd_bootcmd=echo Trying load from SD ..;" \
206 "mmcinfo && mmc read $load_addr " \
207 "$kernel_addr_sd $kernel_size_sd && " \
208 "env exists secureboot && mmc read $kernelheader_addr_r " \
209 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
210 " && esbc_validate ${kernelheader_addr_r};" \
211 "bootm $load_addr#$board\0"
212
213
214#define CONFIG_SYS_CBSIZE 256
215#define CONFIG_SYS_PBSIZE \
216 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
217#define CONFIG_SYS_MAXARGS 16
218#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
219
220#define CONFIG_SYS_LOAD_ADDR 0x82000000
221
222#define CONFIG_LS102XA_STREAM_ID
223
224#define CONFIG_SYS_INIT_SP_OFFSET \
225 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
226#define CONFIG_SYS_INIT_SP_ADDR \
227 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
228
229#ifdef CONFIG_SPL_BUILD
230#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
231#else
232#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
233#endif
234
235
236#define CONFIG_ENV_OVERWRITE
237
238#if defined(CONFIG_SD_BOOT)
239#define CONFIG_SYS_MMC_ENV_DEV 0
240#endif
241
242#define CONFIG_SYS_BOOTM_LEN 0x8000000
243
244#endif
245
