1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 */ 5 6#ifndef __LS1043AQDS_H__ 7#define __LS1043AQDS_H__ 8 9#include "ls1043a_common.h" 10 11#ifndef __ASSEMBLY__ 12unsigned long get_board_sys_clk(void); 13unsigned long get_board_ddr_clk(void); 14#endif 15 16#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 17#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 18 19#define CONFIG_SKIP_LOWLEVEL_INIT 20 21#define CONFIG_LAYERSCAPE_NS_ACCESS 22 23#define CONFIG_DIMM_SLOTS_PER_CTLR 1 24/* Physical Memory Map */ 25#define CONFIG_CHIP_SELECTS_PER_CTRL 4 26 27#define CONFIG_DDR_SPD 28#define SPD_EEPROM_ADDRESS 0x51 29#define CONFIG_SYS_SPD_BUS_NUM 0 30 31#define CONFIG_DDR_ECC 32#ifdef CONFIG_DDR_ECC 33#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 34#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 35#endif 36 37#ifdef CONFIG_SYS_DPAA_FMAN 38#define CONFIG_PHY_VITESSE 39#define CONFIG_PHY_REALTEK 40#define CONFIG_PHYLIB_10G 41#define RGMII_PHY1_ADDR 0x1 42#define RGMII_PHY2_ADDR 0x2 43#define SGMII_CARD_PORT1_PHY_ADDR 0x1C 44#define SGMII_CARD_PORT2_PHY_ADDR 0x1D 45#define SGMII_CARD_PORT3_PHY_ADDR 0x1E 46#define SGMII_CARD_PORT4_PHY_ADDR 0x1F 47/* PHY address on QSGMII riser card on slot 1 */ 48#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 49#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 50#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 51#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 52/* PHY address on QSGMII riser card on slot 2 */ 53#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 54#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 55#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 56#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 57#endif 58 59#ifdef CONFIG_RAMBOOT_PBL 60#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 61#endif 62 63#ifdef CONFIG_NAND_BOOT 64#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 65#endif 66 67#ifdef CONFIG_SD_BOOT 68#ifdef CONFIG_SD_BOOT_QSPI 69#define CONFIG_SYS_FSL_PBL_RCW \ 70 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg 71#else 72#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 73#endif 74#endif 75 76/* LPUART */ 77#ifdef CONFIG_LPUART 78#define CONFIG_LPUART_32B_REG 79#endif 80 81/* SATA */ 82#define CONFIG_SCSI_AHCI_PLAT 83 84/* EEPROM */ 85#define CONFIG_ID_EEPROM 86#define CONFIG_SYS_I2C_EEPROM_NXID 87#define CONFIG_SYS_EEPROM_BUS_NUM 0 88#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 89#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 90#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 91#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 92 93#define CONFIG_SYS_SATA AHCI_BASE_ADDR 94 95#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 96#define CONFIG_SYS_SCSI_MAX_LUN 1 97#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 98 CONFIG_SYS_SCSI_MAX_LUN) 99 100/* 101 * IFC Definitions 102 */ 103#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 104#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 105#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 106 CSPR_PORT_SIZE_16 | \ 107 CSPR_MSEL_NOR | \ 108 CSPR_V) 109#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 110#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 111 + 0x8000000) | \ 112 CSPR_PORT_SIZE_16 | \ 113 CSPR_MSEL_NOR | \ 114 CSPR_V) 115#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 116 117#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 118 CSOR_NOR_TRHZ_80) 119#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 120 FTIM0_NOR_TEADC(0x5) | \ 121 FTIM0_NOR_TEAHC(0x5)) 122#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 123 FTIM1_NOR_TRAD_NOR(0x1a) | \ 124 FTIM1_NOR_TSEQRAD_NOR(0x13)) 125#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 126 FTIM2_NOR_TCH(0x4) | \ 127 FTIM2_NOR_TWPH(0xe) | \ 128 FTIM2_NOR_TWP(0x1c)) 129#define CONFIG_SYS_NOR_FTIM3 0 130 131#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 132#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 133#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 134#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 135 136#define CONFIG_SYS_FLASH_EMPTY_INFO 137#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 138 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 139 140#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 141#define CONFIG_SYS_WRITE_SWAPPED_DATA 142 143/* 144 * NAND Flash Definitions 145 */ 146#define CONFIG_NAND_FSL_IFC 147 148#define CONFIG_SYS_NAND_BASE 0x7e800000 149#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 150 151#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 152 153#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 154 | CSPR_PORT_SIZE_8 \ 155 | CSPR_MSEL_NAND \ 156 | CSPR_V) 157#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 158#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 159 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 160 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 161 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 162 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 163 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 164 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 165 166#define CONFIG_SYS_NAND_ONFI_DETECTION 167 168#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 169 FTIM0_NAND_TWP(0x18) | \ 170 FTIM0_NAND_TWCHT(0x7) | \ 171 FTIM0_NAND_TWH(0xa)) 172#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 173 FTIM1_NAND_TWBE(0x39) | \ 174 FTIM1_NAND_TRR(0xe) | \ 175 FTIM1_NAND_TRP(0x18)) 176#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 177 FTIM2_NAND_TREH(0xa) | \ 178 FTIM2_NAND_TWHRE(0x1e)) 179#define CONFIG_SYS_NAND_FTIM3 0x0 180 181#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 182#define CONFIG_SYS_MAX_NAND_DEVICE 1 183#define CONFIG_MTD_NAND_VERIFY_WRITE 184 185#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 186#endif 187 188#ifdef CONFIG_NAND_BOOT 189#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 190#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 191#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 192#endif 193 194#if defined(CONFIG_TFABOOT) || \ 195 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 196#define CONFIG_QIXIS_I2C_ACCESS 197#define CONFIG_SYS_I2C_EARLY_INIT 198#endif 199 200/* 201 * QIXIS Definitions 202 */ 203#define CONFIG_FSL_QIXIS 204 205#ifdef CONFIG_FSL_QIXIS 206#define QIXIS_BASE 0x7fb00000 207#define QIXIS_BASE_PHYS QIXIS_BASE 208#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 209#define QIXIS_LBMAP_SWITCH 6 210#define QIXIS_LBMAP_MASK 0x0f 211#define QIXIS_LBMAP_SHIFT 0 212#define QIXIS_LBMAP_DFLTBANK 0x00 213#define QIXIS_LBMAP_ALTBANK 0x04 214#define QIXIS_LBMAP_NAND 0x09 215#define QIXIS_LBMAP_SD 0x00 216#define QIXIS_LBMAP_SD_QSPI 0xff 217#define QIXIS_LBMAP_QSPI 0xff 218#define QIXIS_RCW_SRC_NAND 0x106 219#define QIXIS_RCW_SRC_SD 0x040 220#define QIXIS_RCW_SRC_QSPI 0x045 221#define QIXIS_RST_CTL_RESET 0x41 222#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 223#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 224#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 225 226#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 227#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 228 CSPR_PORT_SIZE_8 | \ 229 CSPR_MSEL_GPCM | \ 230 CSPR_V) 231#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 232#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 233 CSOR_NOR_NOR_MODE_AVD_NOR | \ 234 CSOR_NOR_TRHZ_80) 235 236/* 237 * QIXIS Timing parameters for IFC GPCM 238 */ 239#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 240 FTIM0_GPCM_TEADC(0x20) | \ 241 FTIM0_GPCM_TEAHC(0x10)) 242#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 243 FTIM1_GPCM_TRAD(0x1f)) 244#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 245 FTIM2_GPCM_TCH(0x8) | \ 246 FTIM2_GPCM_TWP(0xf0)) 247#define CONFIG_SYS_FPGA_FTIM3 0x0 248#endif 249 250#ifdef CONFIG_TFABOOT 251#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 252#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 253#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 254#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 255#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 256#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 257#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 258#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 259#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 260#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 261#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 262#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 263#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 264#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 265#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 266#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 267#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 268#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 269#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 270#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 271#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 272#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 273#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 274#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 275#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 276#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 277#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 278#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 279#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 280#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 281#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 282#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 283#else 284#ifdef CONFIG_NAND_BOOT 285#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 286#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 287#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 288#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 289#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 290#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 291#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 292#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 293#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 294#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 295#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 296#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 297#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 298#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 299#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 300#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 301#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 302#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 303#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 304#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 305#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 306#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 307#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 308#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 309#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 310#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 311#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 312#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 313#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 314#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 315#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 316#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 317#else 318#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 319#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 320#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 321#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 322#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 323#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 324#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 325#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 326#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 327#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 328#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 329#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 330#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 331#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 332#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 333#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 334#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 335#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 336#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 337#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 338#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 339#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 340#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 341#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 342#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 343#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 344#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 345#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 346#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 347#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 348#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 349#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 350#endif 351#endif 352 353/* 354 * I2C bus multiplexer 355 */ 356#define I2C_MUX_PCA_ADDR_PRI 0x77 357#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 358#define I2C_RETIMER_ADDR 0x18 359#define I2C_MUX_CH_DEFAULT 0x8 360#define I2C_MUX_CH_CH7301 0xC 361#define I2C_MUX_CH5 0xD 362#define I2C_MUX_CH7 0xF 363 364#define I2C_MUX_CH_VOL_MONITOR 0xa 365 366/* Voltage monitor on channel 2*/ 367#define I2C_VOL_MONITOR_ADDR 0x40 368#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 369#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 370#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 371 372#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 373#ifndef CONFIG_SPL_BUILD 374#define CONFIG_VID 375#endif 376#define CONFIG_VOL_MONITOR_IR36021_SET 377#define CONFIG_VOL_MONITOR_INA220 378/* The lowest and highest voltage allowed for LS1043AQDS */ 379#define VDD_MV_MIN 819 380#define VDD_MV_MAX 1212 381 382/* QSPI device */ 383#if defined(CONFIG_TFABOOT) || \ 384 (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)) 385#ifdef CONFIG_FSL_QSPI 386#define CONFIG_SPI_FLASH_SPANSION 387#define FSL_QSPI_FLASH_SIZE (1 << 24) 388#define FSL_QSPI_FLASH_NUM 2 389#endif 390#endif 391 392/* 393 * Miscellaneous configurable options 394 */ 395 396#define CONFIG_SYS_MEMTEST_START 0x80000000 397#define CONFIG_SYS_MEMTEST_END 0x9fffffff 398 399#define CONFIG_SYS_HZ 1000 400 401#define CONFIG_SYS_INIT_SP_OFFSET \ 402 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 403 404#ifdef CONFIG_SPL_BUILD 405#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 406#else 407#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 408#endif 409 410/* 411 * Environment 412 */ 413#define CONFIG_ENV_OVERWRITE 414 415#ifdef CONFIG_TFABOOT 416#define CONFIG_SYS_MMC_ENV_DEV 0 417#else 418#ifdef CONFIG_NAND_BOOT 419#elif defined(CONFIG_SD_BOOT) 420#define CONFIG_SYS_MMC_ENV_DEV 0 421#endif 422#endif 423 424#define CONFIG_CMDLINE_TAG 425 426#include <asm/fsl_secure_boot.h> 427 428#endif /* __LS1043AQDS_H__ */ 429