1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2015 Freescale Semiconductor 4 */ 5 6#ifndef __LS1043ARDB_H__ 7#define __LS1043ARDB_H__ 8 9#include "ls1043a_common.h" 10 11#define CONFIG_SYS_CLK_FREQ 100000000 12#define CONFIG_DDR_CLK_FREQ 100000000 13 14#define CONFIG_LAYERSCAPE_NS_ACCESS 15 16#define CONFIG_DIMM_SLOTS_PER_CTLR 1 17/* Physical Memory Map */ 18#define CONFIG_CHIP_SELECTS_PER_CTRL 4 19 20#define CONFIG_SYS_SPD_BUS_NUM 0 21 22#ifndef CONFIG_SPL 23#define CONFIG_SYS_DDR_RAW_TIMING 24#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 25#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 26#endif 27 28#ifdef CONFIG_RAMBOOT_PBL 29#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg 30#endif 31 32#ifdef CONFIG_NAND_BOOT 33#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg 34#endif 35 36#ifdef CONFIG_SD_BOOT 37#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg 38#define CONFIG_CMD_SPL 39#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 40#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 41#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 42#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30 43#endif 44 45/* 46 * NOR Flash Definitions 47 */ 48#define CONFIG_SYS_NOR_CSPR_EXT (0x0) 49#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 50#define CONFIG_SYS_NOR_CSPR \ 51 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 52 CSPR_PORT_SIZE_16 | \ 53 CSPR_MSEL_NOR | \ 54 CSPR_V) 55 56/* NOR Flash Timing Params */ 57#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 58 CSOR_NOR_TRHZ_80) 59#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 60 FTIM0_NOR_TEADC(0x1) | \ 61 FTIM0_NOR_TAVDS(0x0) | \ 62 FTIM0_NOR_TEAHC(0xc)) 63#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ 64 FTIM1_NOR_TRAD_NOR(0xb) | \ 65 FTIM1_NOR_TSEQRAD_NOR(0x9)) 66#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ 67 FTIM2_NOR_TCH(0x4) | \ 68 FTIM2_NOR_TWPH(0x8) | \ 69 FTIM2_NOR_TWP(0x10)) 70#define CONFIG_SYS_NOR_FTIM3 0 71#define CONFIG_SYS_IFC_CCR 0x01000000 72 73#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 74#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 75#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 76#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 77 78#define CONFIG_SYS_FLASH_EMPTY_INFO 79#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 80 81#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 82#define CONFIG_SYS_WRITE_SWAPPED_DATA 83 84/* 85 * NAND Flash Definitions 86 */ 87#ifndef SPL_NO_IFC 88#define CONFIG_NAND_FSL_IFC 89#endif 90 91#define CONFIG_SYS_NAND_BASE 0x7e800000 92#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 93 94#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 95#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 96 | CSPR_PORT_SIZE_8 \ 97 | CSPR_MSEL_NAND \ 98 | CSPR_V) 99#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 100#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 101 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 102 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 103 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 104 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 105 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 106 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 107 108#define CONFIG_SYS_NAND_ONFI_DETECTION 109 110#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 111 FTIM0_NAND_TWP(0x18) | \ 112 FTIM0_NAND_TWCHT(0x7) | \ 113 FTIM0_NAND_TWH(0xa)) 114#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 115 FTIM1_NAND_TWBE(0x39) | \ 116 FTIM1_NAND_TRR(0xe) | \ 117 FTIM1_NAND_TRP(0x18)) 118#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 119 FTIM2_NAND_TREH(0xa) | \ 120 FTIM2_NAND_TWHRE(0x1e)) 121#define CONFIG_SYS_NAND_FTIM3 0x0 122 123#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 124#define CONFIG_SYS_MAX_NAND_DEVICE 1 125#define CONFIG_MTD_NAND_VERIFY_WRITE 126 127#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 128 129#ifdef CONFIG_NAND_BOOT 130#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 131#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 132#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) 133#endif 134 135/* 136 * CPLD 137 */ 138#define CONFIG_SYS_CPLD_BASE 0x7fb00000 139#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 140 141#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 142#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 143 CSPR_PORT_SIZE_8 | \ 144 CSPR_MSEL_GPCM | \ 145 CSPR_V) 146#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 147#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 148 CSOR_NOR_NOR_MODE_AVD_NOR | \ 149 CSOR_NOR_TRHZ_80) 150 151/* CPLD Timing parameters for IFC GPCM */ 152#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 153 FTIM0_GPCM_TEADC(0xf) | \ 154 FTIM0_GPCM_TEAHC(0xf)) 155#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 156 FTIM1_GPCM_TRAD(0x3f)) 157#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 158 FTIM2_GPCM_TCH(0xf) | \ 159 FTIM2_GPCM_TWP(0xff)) 160#define CONFIG_SYS_CPLD_FTIM3 0x0 161 162/* IFC Timing Params */ 163#ifdef CONFIG_TFABOOT 164#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 165#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 166#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 167#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 168#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 169#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 170#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 171#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 172 173#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 174#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 175#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 176#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 177#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 178#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 179#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 180#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 181#else 182#ifdef CONFIG_NAND_BOOT 183#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 184#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 185#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 186#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 187#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 188#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 189#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 190#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 191 192#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 193#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 194#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 195#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 196#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 197#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 198#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 199#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 200#else 201#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 202#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 203#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 204#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 205#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 206#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 207#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 208#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 209 210#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 211#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 212#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 213#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 214#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 215#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 216#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 217#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 218#endif 219#endif 220 221#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 222#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 223#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 224#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 225#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 226#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 227#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 228#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 229 230/* EEPROM */ 231#ifndef SPL_NO_EEPROM 232#define CONFIG_ID_EEPROM 233#define CONFIG_SYS_I2C_EEPROM_NXID 234#define CONFIG_SYS_EEPROM_BUS_NUM 0 235#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 236#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 237#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 238#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 239#endif 240 241/* 242 * Environment 243 */ 244#ifndef SPL_NO_ENV 245#define CONFIG_ENV_OVERWRITE 246#endif 247 248#ifdef CONFIG_TFABOOT 249#define CONFIG_SYS_MMC_ENV_DEV 0 250#else 251#if defined(CONFIG_NAND_BOOT) 252#elif defined(CONFIG_SD_BOOT) 253#define CONFIG_SYS_MMC_ENV_DEV 0 254#endif 255#endif 256 257/* FMan */ 258#ifndef SPL_NO_FMAN 259#define AQR105_IRQ_MASK 0x40000000 260 261#ifdef CONFIG_NET 262#define CONFIG_PHY_VITESSE 263#define CONFIG_PHY_REALTEK 264#endif 265 266#ifdef CONFIG_SYS_DPAA_FMAN 267#define RGMII_PHY1_ADDR 0x1 268#define RGMII_PHY2_ADDR 0x2 269 270#define QSGMII_PORT1_PHY_ADDR 0x4 271#define QSGMII_PORT2_PHY_ADDR 0x5 272#define QSGMII_PORT3_PHY_ADDR 0x6 273#define QSGMII_PORT4_PHY_ADDR 0x7 274 275#define FM1_10GEC1_PHY_ADDR 0x1 276 277#define CONFIG_ETHPRIME "FM1@DTSEC3" 278#endif 279#endif 280 281/* SATA */ 282#ifndef SPL_NO_SATA 283#ifndef CONFIG_CMD_EXT2 284#define CONFIG_CMD_EXT2 285#endif 286#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 287#define CONFIG_SYS_SCSI_MAX_LUN 2 288#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 289 CONFIG_SYS_SCSI_MAX_LUN) 290#define SCSI_VEND_ID 0x1b4b 291#define SCSI_DEV_ID 0x9170 292#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} 293#endif 294 295#include <asm/fsl_secure_boot.h> 296 297#endif /* __LS1043ARDB_H__ */ 298