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5
6
7#ifndef __LS1046A_COMMON_H
8#define __LS1046A_COMMON_H
9
10
11#ifdef CONFIG_SPL_BUILD
12#define SPL_NO_QBMAN
13#define SPL_NO_FMAN
14#define SPL_NO_ENV
15#define SPL_NO_MISC
16#define SPL_NO_QSPI
17#define SPL_NO_USB
18#define SPL_NO_SATA
19#endif
20#if defined(CONFIG_SPL_BUILD) && \
21 (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
22#define SPL_NO_MMC
23#endif
24#if defined(CONFIG_SPL_BUILD) && \
25 !defined(CONFIG_SPL_FSL_LS_PPA)
26#define SPL_NO_IFC
27#endif
28
29#define CONFIG_REMAKE_ELF
30#define CONFIG_GICV2
31
32#include <asm/arch/config.h>
33#include <asm/arch/stream_id_lsch2.h>
34
35
36#ifdef CONFIG_TFABOOT
37#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
38#else
39#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
40#endif
41
42#define CONFIG_SKIP_LOWLEVEL_INIT
43
44#define CONFIG_VERY_BIG_RAM
45#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
46#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
48#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
49
50#define CPU_RELEASE_ADDR secondary_boot_func
51
52
53#define COUNTER_FREQUENCY 25000000
54
55
56#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
57
58
59#define CONFIG_SYS_NS16550_SERIAL
60#define CONFIG_SYS_NS16550_REG_SIZE 1
61#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
62
63#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
64
65
66#ifdef CONFIG_SD_BOOT
67#define CONFIG_SPL_MAX_SIZE 0x1f000
68#define CONFIG_SPL_STACK 0x10020000
69#define CONFIG_SPL_PAD_TO 0x21000
70#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
71#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
72#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
73 CONFIG_SPL_BSS_MAX_SIZE)
74#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
75
76#ifdef CONFIG_NXP_ESBC
77#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
78
79
80
81
82
83
84#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
85#else
86#define CONFIG_SYS_MONITOR_LEN 0x100000
87#endif
88#endif
89
90#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
91#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
92#define CONFIG_SPL_MAX_SIZE 0x1f000
93#define CONFIG_SPL_STACK 0x10020000
94#define CONFIG_SPL_PAD_TO 0x20000
95#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
96#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
97#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
98 CONFIG_SPL_BSS_MAX_SIZE)
99#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
100#define CONFIG_SYS_MONITOR_LEN 0x100000
101#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
102#endif
103
104
105#ifdef CONFIG_NAND_BOOT
106#define CONFIG_SPL_PBL_PAD
107#define CONFIG_SPL_LIBCOMMON_SUPPORT
108#define CONFIG_SPL_LIBGENERIC_SUPPORT
109#define CONFIG_SPL_ENV_SUPPORT
110#define CONFIG_SPL_WATCHDOG_SUPPORT
111#define CONFIG_SPL_I2C_SUPPORT
112#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
113
114#define CONFIG_SPL_NAND_SUPPORT
115#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
116#define CONFIG_SPL_MAX_SIZE 0x17000
117#define CONFIG_SPL_STACK 0x1001f000
118#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
119#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
120
121#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
122#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
123#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
124 CONFIG_SPL_BSS_MAX_SIZE)
125#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
126#define CONFIG_SYS_MONITOR_LEN 0xa0000
127#endif
128
129
130#define CONFIG_SYS_I2C
131
132
133#define CONFIG_PCIE1
134#define CONFIG_PCIE2
135#define CONFIG_PCIE3
136
137#ifdef CONFIG_PCI
138#define CONFIG_PCI_SCAN_SHOW
139#endif
140
141
142#ifndef SPL_NO_SATA
143#define CONFIG_SCSI_AHCI_PLAT
144
145#define CONFIG_SYS_SATA AHCI_BASE_ADDR
146
147#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
148#define CONFIG_SYS_SCSI_MAX_LUN 1
149#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
150 CONFIG_SYS_SCSI_MAX_LUN)
151#endif
152
153
154
155
156#ifndef SPL_NO_MMC
157#ifdef CONFIG_MMC
158#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
159#endif
160#endif
161
162
163#ifndef SPL_NO_FMAN
164#define CONFIG_SYS_DPAA_FMAN
165#ifdef CONFIG_SYS_DPAA_FMAN
166#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
167#endif
168
169#ifdef CONFIG_TFABOOT
170#define CONFIG_SYS_FMAN_FW_ADDR 0x900000
171#else
172#ifdef CONFIG_SD_BOOT
173
174
175
176
177
178#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
179#elif defined(CONFIG_QSPI_BOOT)
180#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
181#elif defined(CONFIG_NAND_BOOT)
182#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
183#else
184#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
185#endif
186#endif
187#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
188#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
189#endif
190
191
192#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
193
194#define CONFIG_HWCONFIG
195#define HWCONFIG_BUFFER_SIZE 128
196
197#ifndef CONFIG_SPL_BUILD
198#define BOOT_TARGET_DEVICES(func) \
199 func(SCSI, scsi, 0) \
200 func(MMC, mmc, 0) \
201 func(USB, usb, 0) \
202 func(DHCP, dhcp, na)
203#include <config_distro_bootcmd.h>
204#endif
205
206#if defined(CONFIG_TARGET_LS1046AFRWY)
207#define LS1046A_BOOT_SRC_AND_HDR\
208 "boot_scripts=ls1046afrwy_boot.scr\0" \
209 "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
210#else
211#define LS1046A_BOOT_SRC_AND_HDR\
212 "boot_scripts=ls1046ardb_boot.scr\0" \
213 "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
214#endif
215#ifndef SPL_NO_MISC
216
217#define CONFIG_EXTRA_ENV_SETTINGS \
218 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
219 "ramdisk_addr=0x800000\0" \
220 "ramdisk_size=0x2000000\0" \
221 "fdt_high=0xffffffffffffffff\0" \
222 "initrd_high=0xffffffffffffffff\0" \
223 "fdt_addr=0x64f00000\0" \
224 "kernel_addr=0x65000000\0" \
225 "scriptaddr=0x80000000\0" \
226 "scripthdraddr=0x80080000\0" \
227 "fdtheader_addr_r=0x80100000\0" \
228 "kernelheader_addr_r=0x80200000\0" \
229 "load_addr=0xa0000000\0" \
230 "kernel_addr_r=0x81000000\0" \
231 "fdt_addr_r=0x90000000\0" \
232 "ramdisk_addr_r=0xa0000000\0" \
233 "kernel_start=0x1000000\0" \
234 "kernelheader_start=0x800000\0" \
235 "kernel_load=0xa0000000\0" \
236 "kernel_size=0x2800000\0" \
237 "kernelheader_size=0x40000\0" \
238 "kernel_addr_sd=0x8000\0" \
239 "kernel_size_sd=0x14000\0" \
240 "kernelhdr_addr_sd=0x4000\0" \
241 "kernelhdr_size_sd=0x10\0" \
242 "console=ttyS0,115200\0" \
243 CONFIG_MTDPARTS_DEFAULT "\0" \
244 BOOTENV \
245 LS1046A_BOOT_SRC_AND_HDR \
246 "scan_dev_for_boot_part=" \
247 "part list ${devtype} ${devnum} devplist; " \
248 "env exists devplist || setenv devplist 1; " \
249 "for distro_bootpart in ${devplist}; do " \
250 "if fstype ${devtype} " \
251 "${devnum}:${distro_bootpart} " \
252 "bootfstype; then " \
253 "run scan_dev_for_boot; " \
254 "fi; " \
255 "done\0" \
256 "boot_a_script=" \
257 "load ${devtype} ${devnum}:${distro_bootpart} " \
258 "${scriptaddr} ${prefix}${script}; " \
259 "env exists secureboot && load ${devtype} " \
260 "${devnum}:${distro_bootpart} " \
261 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
262 "env exists secureboot " \
263 "&& esbc_validate ${scripthdraddr};" \
264 "source ${scriptaddr}\0" \
265 "qspi_bootcmd=echo Trying load from qspi..;" \
266 "sf probe && sf read $load_addr " \
267 "$kernel_start $kernel_size; env exists secureboot " \
268 "&& sf read $kernelheader_addr_r $kernelheader_start " \
269 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
270 "bootm $load_addr#$board\0" \
271 "sd_bootcmd=echo Trying load from SD ..;" \
272 "mmcinfo; mmc read $load_addr " \
273 "$kernel_addr_sd $kernel_size_sd && " \
274 "env exists secureboot && mmc read $kernelheader_addr_r " \
275 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
276 " && esbc_validate ${kernelheader_addr_r};" \
277 "bootm $load_addr#$board\0"
278
279#endif
280
281
282#define CONFIG_SYS_CBSIZE 512
283
284#define CONFIG_SYS_MAXARGS 64
285
286#define CONFIG_SYS_BOOTM_LEN (64 << 20)
287
288#include <asm/arch/soc.h>
289
290#endif
291