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6
7#ifndef __LS2_RDB_H
8#define __LS2_RDB_H
9
10#include "ls2080a_common.h"
11
12#ifdef CONFIG_FSL_QSPI
13#ifdef CONFIG_TARGET_LS2081ARDB
14#define CONFIG_QIXIS_I2C_ACCESS
15#endif
16#ifndef CONFIG_DM_I2C
17#define CONFIG_SYS_I2C_EARLY_INIT
18#endif
19#endif
20
21#define I2C_MUX_CH_VOL_MONITOR 0xa
22#define I2C_VOL_MONITOR_ADDR 0x38
23#define CONFIG_VOL_MONITOR_IR36021_READ
24#define CONFIG_VOL_MONITOR_IR36021_SET
25
26#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
27#ifndef CONFIG_SPL_BUILD
28#define CONFIG_VID
29#endif
30
31#define IR_VDD_STEP_DOWN 5
32#define IR_VDD_STEP_UP 5
33
34#define VDD_MV_MIN 819
35#define VDD_MV_MAX 1212
36
37#ifndef __ASSEMBLY__
38unsigned long get_board_sys_clk(void);
39#endif
40
41#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
42#define CONFIG_DDR_CLK_FREQ 133333333
43#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
44
45#define CONFIG_DDR_SPD
46#define CONFIG_DDR_ECC
47#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
49#define SPD_EEPROM_ADDRESS1 0x51
50#define SPD_EEPROM_ADDRESS2 0x52
51#define SPD_EEPROM_ADDRESS3 0x53
52#define SPD_EEPROM_ADDRESS4 0x54
53#define SPD_EEPROM_ADDRESS5 0x55
54#define SPD_EEPROM_ADDRESS6 0x56
55#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
56#define CONFIG_SYS_SPD_BUS_NUM 0
57#define CONFIG_DIMM_SLOTS_PER_CTLR 2
58#define CONFIG_CHIP_SELECTS_PER_CTRL 4
59#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
60#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
61#endif
62
63
64#define CONFIG_SCSI_AHCI_PLAT
65
66#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
67#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
68
69#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
70#define CONFIG_SYS_SCSI_MAX_LUN 1
71#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
72 CONFIG_SYS_SCSI_MAX_LUN)
73#ifdef CONFIG_TFABOOT
74#define CONFIG_SYS_MMC_ENV_DEV 0
75#endif
76
77#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
78
79#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
80#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
81#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
82
83#define CONFIG_SYS_NOR0_CSPR \
84 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
85 CSPR_PORT_SIZE_16 | \
86 CSPR_MSEL_NOR | \
87 CSPR_V)
88#define CONFIG_SYS_NOR0_CSPR_EARLY \
89 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
90 CSPR_PORT_SIZE_16 | \
91 CSPR_MSEL_NOR | \
92 CSPR_V)
93#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
94#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
95 FTIM0_NOR_TEADC(0x5) | \
96 FTIM0_NOR_TEAHC(0x5))
97#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
98 FTIM1_NOR_TRAD_NOR(0x1a) |\
99 FTIM1_NOR_TSEQRAD_NOR(0x13))
100#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
101 FTIM2_NOR_TCH(0x4) | \
102 FTIM2_NOR_TWPH(0x0E) | \
103 FTIM2_NOR_TWP(0x1c))
104#define CONFIG_SYS_NOR_FTIM3 0x04000000
105#define CONFIG_SYS_IFC_CCR 0x01000000
106
107#ifdef CONFIG_MTD_NOR_FLASH
108#define CONFIG_SYS_FLASH_QUIET_TEST
109#define CONFIG_FLASH_SHOW_PROGRESS 45
110
111#define CONFIG_SYS_MAX_FLASH_BANKS 1
112#define CONFIG_SYS_MAX_FLASH_SECT 1024
113#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
114#define CONFIG_SYS_FLASH_WRITE_TOUT 500
115
116#define CONFIG_SYS_FLASH_EMPTY_INFO
117#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
118 CONFIG_SYS_FLASH_BASE + 0x40000000}
119#endif
120
121#define CONFIG_NAND_FSL_IFC
122#define CONFIG_SYS_NAND_MAX_ECCPOS 256
123#define CONFIG_SYS_NAND_MAX_OOBFREE 2
124
125#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
126#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
127 | CSPR_PORT_SIZE_8 \
128 | CSPR_MSEL_NAND \
129 | CSPR_V)
130#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
131
132#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
133 | CSOR_NAND_ECC_DEC_EN \
134 | CSOR_NAND_ECC_MODE_4 \
135 | CSOR_NAND_RAL_3 \
136 | CSOR_NAND_PGS_4K \
137 | CSOR_NAND_SPRZ_224 \
138 | CSOR_NAND_PB(128))
139
140#define CONFIG_SYS_NAND_ONFI_DETECTION
141
142
143#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
144 FTIM0_NAND_TWP(0x30) | \
145 FTIM0_NAND_TWCHT(0x0e) | \
146 FTIM0_NAND_TWH(0x14))
147#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
148 FTIM1_NAND_TWBE(0xab) | \
149 FTIM1_NAND_TRR(0x1c) | \
150 FTIM1_NAND_TRP(0x30))
151#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
152 FTIM2_NAND_TREH(0x14) | \
153 FTIM2_NAND_TWHRE(0x3c))
154#define CONFIG_SYS_NAND_FTIM3 0x0
155
156#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
157#define CONFIG_SYS_MAX_NAND_DEVICE 1
158#define CONFIG_MTD_NAND_VERIFY_WRITE
159
160#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
161#define CONFIG_FSL_QIXIS
162#define QIXIS_LBMAP_SWITCH 0x06
163#define QIXIS_LBMAP_MASK 0x0f
164#define QIXIS_LBMAP_SHIFT 0
165#define QIXIS_LBMAP_DFLTBANK 0x00
166#define QIXIS_LBMAP_ALTBANK 0x04
167#define QIXIS_LBMAP_NAND 0x09
168#define QIXIS_RST_CTL_RESET 0x31
169#define QIXIS_RST_CTL_RESET_EN 0x30
170#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
171#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
172#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
173#define QIXIS_RCW_SRC_NAND 0x119
174#define QIXIS_RST_FORCE_MEM 0x01
175
176#define CONFIG_SYS_CSPR3_EXT (0x0)
177#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
178 | CSPR_PORT_SIZE_8 \
179 | CSPR_MSEL_GPCM \
180 | CSPR_V)
181#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
182 | CSPR_PORT_SIZE_8 \
183 | CSPR_MSEL_GPCM \
184 | CSPR_V)
185
186#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
187#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
188
189#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
190 FTIM0_GPCM_TEADC(0x0e) | \
191 FTIM0_GPCM_TEAHC(0x0e))
192#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
193 FTIM1_GPCM_TRAD(0x3f))
194#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
195 FTIM2_GPCM_TCH(0xf) | \
196 FTIM2_GPCM_TWP(0x3E))
197#define CONFIG_SYS_CS3_FTIM3 0x0
198
199#if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
200#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
201#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
202#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
203#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
204#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
205#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
206#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
207#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
208#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
209#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
210#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
211#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
212#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
213#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
214#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
215#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
216#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
217
218#define CONFIG_SPL_PAD_TO 0x80000
219#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
220#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
221#else
222#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
223#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
224#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
225#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
226#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
227#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
228#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
229#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
230#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
231#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
232#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
233#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
234#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
235#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
236#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
237#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
238#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
239#endif
240
241
242#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
243#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
244#endif
245#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
246
247#ifdef CONFIG_TARGET_LS2081ARDB
248#define CONFIG_FSL_QIXIS
249#define QIXIS_QMAP_MASK 0x07
250#define QIXIS_QMAP_SHIFT 5
251#define QIXIS_LBMAP_DFLTBANK 0x00
252#define QIXIS_LBMAP_QSPI 0x00
253#define QIXIS_RCW_SRC_QSPI 0x62
254#define QIXIS_LBMAP_ALTBANK 0x20
255#define QIXIS_RST_CTL_RESET 0x31
256#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
257#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
258#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
259#define QIXIS_LBMAP_MASK 0x0f
260#define QIXIS_RST_CTL_RESET_EN 0x30
261#endif
262
263
264
265
266#ifdef CONFIG_TARGET_LS2081ARDB
267#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
268#endif
269#define I2C_MUX_PCA_ADDR 0x75
270#define I2C_MUX_PCA_ADDR_PRI 0x75
271
272
273#define I2C_MUX_CH_DEFAULT 0x8
274
275
276#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
277#ifdef CONFIG_FSL_DSPI
278#define CONFIG_SPI_FLASH_STMICRO
279#endif
280#define FSL_QSPI_FLASH_SIZE SZ_64M
281#define FSL_QSPI_FLASH_NUM 2
282#endif
283
284
285
286
287#define RTC
288#ifdef CONFIG_TARGET_LS2081ARDB
289#define CONFIG_RTC_PCF8563 1
290#define CONFIG_SYS_I2C_RTC_ADDR 0x51
291#else
292#define CONFIG_RTC_DS3231 1
293#define CONFIG_SYS_I2C_RTC_ADDR 0x68
294#endif
295
296
297#define CONFIG_ID_EEPROM
298#define CONFIG_SYS_I2C_EEPROM_NXID
299#define CONFIG_SYS_EEPROM_BUS_NUM 0
300#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
301#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
302#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
303#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
304
305#define CONFIG_FSL_MEMAC
306
307#ifdef CONFIG_PCI
308#define CONFIG_PCI_SCAN_SHOW
309#endif
310
311
312#ifdef CONFIG_MMC
313#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
314#endif
315
316#define BOOT_TARGET_DEVICES(func) \
317 func(USB, usb, 0) \
318 func(MMC, mmc, 0) \
319 func(SCSI, scsi, 0) \
320 func(DHCP, dhcp, na)
321#include <config_distro_bootcmd.h>
322
323#ifdef CONFIG_TFABOOT
324#define QSPI_MC_INIT_CMD \
325 "env exists secureboot && " \
326 "esbc_validate 0x20700000 && " \
327 "esbc_validate 0x20740000;" \
328 "fsl_mc start mc 0x20a00000 0x20e00000 \0"
329#define SD_MC_INIT_CMD \
330 "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
331 "mmc read 0x80e00000 0x7000 0x800;" \
332 "env exists secureboot && " \
333 "mmc read 0x80700000 0x3800 0x10 && " \
334 "mmc read 0x80740000 0x3A00 0x10 && " \
335 "esbc_validate 0x80700000 && " \
336 "esbc_validate 0x80740000 ;" \
337 "fsl_mc start mc 0x80a00000 0x80e00000\0"
338#define IFC_MC_INIT_CMD \
339 "env exists secureboot && " \
340 "esbc_validate 0x580700000 && " \
341 "esbc_validate 0x580740000; " \
342 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
343#else
344#ifdef CONFIG_QSPI_BOOT
345#define MC_INIT_CMD \
346 "mcinitcmd=env exists secureboot && " \
347 "esbc_validate 0x20700000 && " \
348 "esbc_validate 0x20740000;" \
349 "fsl_mc start mc 0x20a00000 0x20e00000 \0"
350#elif defined(CONFIG_SD_BOOT)
351#define MC_INIT_CMD \
352 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
353 "mmc read 0x80100000 0x7000 0x800;" \
354 "env exists secureboot && " \
355 "mmc read 0x80700000 0x3800 0x10 && " \
356 "mmc read 0x80740000 0x3A00 0x10 && " \
357 "esbc_validate 0x80700000 && " \
358 "esbc_validate 0x80740000 ;" \
359 "fsl_mc start mc 0x80000000 0x80100000\0" \
360 "mcmemsize=0x70000000\0"
361#else
362#define MC_INIT_CMD \
363 "mcinitcmd=env exists secureboot && " \
364 "esbc_validate 0x580700000 && " \
365 "esbc_validate 0x580740000; " \
366 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
367#endif
368#endif
369
370
371#undef CONFIG_EXTRA_ENV_SETTINGS
372#ifdef CONFIG_TFABOOT
373#define CONFIG_EXTRA_ENV_SETTINGS \
374 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
375 "ramdisk_addr=0x800000\0" \
376 "ramdisk_size=0x2000000\0" \
377 "fdt_high=0xa0000000\0" \
378 "initrd_high=0xffffffffffffffff\0" \
379 "fdt_addr=0x64f00000\0" \
380 "kernel_addr=0x581000000\0" \
381 "kernel_start=0x1000000\0" \
382 "kernelheader_start=0x800000\0" \
383 "scriptaddr=0x80000000\0" \
384 "scripthdraddr=0x80080000\0" \
385 "fdtheader_addr_r=0x80100000\0" \
386 "kernelheader_addr_r=0x80200000\0" \
387 "kernelheader_addr=0x580800000\0" \
388 "kernel_addr_r=0x81000000\0" \
389 "kernelheader_size=0x40000\0" \
390 "fdt_addr_r=0x90000000\0" \
391 "load_addr=0xa0000000\0" \
392 "kernel_size=0x2800000\0" \
393 "kernel_addr_sd=0x8000\0" \
394 "kernel_size_sd=0x14000\0" \
395 "console=ttyAMA0,38400n8\0" \
396 "mcmemsize=0x70000000\0" \
397 "sd_bootcmd=echo Trying load from SD ..;" \
398 "mmcinfo; mmc read $load_addr " \
399 "$kernel_addr_sd $kernel_size_sd && " \
400 "bootm $load_addr#$board\0" \
401 QSPI_MC_INIT_CMD \
402 BOOTENV \
403 "boot_scripts=ls2088ardb_boot.scr\0" \
404 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
405 "scan_dev_for_boot_part=" \
406 "part list ${devtype} ${devnum} devplist; " \
407 "env exists devplist || setenv devplist 1; " \
408 "for distro_bootpart in ${devplist}; do " \
409 "if fstype ${devtype} " \
410 "${devnum}:${distro_bootpart} " \
411 "bootfstype; then " \
412 "run scan_dev_for_boot; " \
413 "fi; " \
414 "done\0" \
415 "boot_a_script=" \
416 "load ${devtype} ${devnum}:${distro_bootpart} " \
417 "${scriptaddr} ${prefix}${script}; " \
418 "env exists secureboot && load ${devtype} " \
419 "${devnum}:${distro_bootpart} " \
420 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
421 "&& esbc_validate ${scripthdraddr};" \
422 "source ${scriptaddr}\0" \
423 "qspi_bootcmd=echo Trying load from qspi..;" \
424 "sf probe && sf read $load_addr " \
425 "$kernel_start $kernel_size ; env exists secureboot &&" \
426 "sf read $kernelheader_addr_r $kernelheader_start " \
427 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
428 " bootm $load_addr#$board\0" \
429 "nor_bootcmd=echo Trying load from nor..;" \
430 "cp.b $kernel_addr $load_addr " \
431 "$kernel_size ; env exists secureboot && " \
432 "cp.b $kernelheader_addr $kernelheader_addr_r " \
433 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
434 "bootm $load_addr#$board\0"
435#else
436#define CONFIG_EXTRA_ENV_SETTINGS \
437 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
438 "ramdisk_addr=0x800000\0" \
439 "ramdisk_size=0x2000000\0" \
440 "fdt_high=0xa0000000\0" \
441 "initrd_high=0xffffffffffffffff\0" \
442 "fdt_addr=0x64f00000\0" \
443 "kernel_addr=0x581000000\0" \
444 "kernel_start=0x1000000\0" \
445 "kernelheader_start=0x800000\0" \
446 "scriptaddr=0x80000000\0" \
447 "scripthdraddr=0x80080000\0" \
448 "fdtheader_addr_r=0x80100000\0" \
449 "kernelheader_addr_r=0x80200000\0" \
450 "kernelheader_addr=0x580800000\0" \
451 "kernel_addr_r=0x81000000\0" \
452 "kernelheader_size=0x40000\0" \
453 "fdt_addr_r=0x90000000\0" \
454 "load_addr=0xa0000000\0" \
455 "kernel_size=0x2800000\0" \
456 "kernel_addr_sd=0x8000\0" \
457 "kernel_size_sd=0x14000\0" \
458 "console=ttyAMA0,38400n8\0" \
459 "mcmemsize=0x70000000\0" \
460 "sd_bootcmd=echo Trying load from SD ..;" \
461 "mmcinfo; mmc read $load_addr " \
462 "$kernel_addr_sd $kernel_size_sd && " \
463 "bootm $load_addr#$board\0" \
464 MC_INIT_CMD \
465 BOOTENV \
466 "boot_scripts=ls2088ardb_boot.scr\0" \
467 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
468 "scan_dev_for_boot_part=" \
469 "part list ${devtype} ${devnum} devplist; " \
470 "env exists devplist || setenv devplist 1; " \
471 "for distro_bootpart in ${devplist}; do " \
472 "if fstype ${devtype} " \
473 "${devnum}:${distro_bootpart} " \
474 "bootfstype; then " \
475 "run scan_dev_for_boot; " \
476 "fi; " \
477 "done\0" \
478 "boot_a_script=" \
479 "load ${devtype} ${devnum}:${distro_bootpart} " \
480 "${scriptaddr} ${prefix}${script}; " \
481 "env exists secureboot && load ${devtype} " \
482 "${devnum}:${distro_bootpart} " \
483 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
484 "env exists secureboot " \
485 "&& esbc_validate ${scripthdraddr};" \
486 "source ${scriptaddr}\0" \
487 "qspi_bootcmd=echo Trying load from qspi..;" \
488 "sf probe && sf read $load_addr " \
489 "$kernel_start $kernel_size ; env exists secureboot &&" \
490 "sf read $kernelheader_addr_r $kernelheader_start " \
491 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
492 " bootm $load_addr#$board\0" \
493 "nor_bootcmd=echo Trying load from nor..;" \
494 "cp.b $kernel_addr $load_addr " \
495 "$kernel_size ; env exists secureboot && " \
496 "cp.b $kernelheader_addr $kernelheader_addr_r " \
497 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
498 "bootm $load_addr#$board\0"
499#endif
500
501#ifdef CONFIG_TFABOOT
502#define QSPI_NOR_BOOTCOMMAND \
503 "env exists mcinitcmd && env exists secureboot "\
504 "&& esbc_validate 0x20780000; " \
505 "env exists mcinitcmd && " \
506 "fsl_mc lazyapply dpl 0x20d00000; " \
507 "run distro_bootcmd;run qspi_bootcmd; " \
508 "env exists secureboot && esbc_halt;"
509
510
511#define SD_BOOTCOMMAND \
512 "env exists mcinitcmd && env exists secureboot "\
513 "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
514 "&& esbc_validate $load_addr; " \
515 "env exists mcinitcmd && run mcinitcmd " \
516 "&& mmc read 0x80d00000 0x6800 0x800 " \
517 "&& fsl_mc lazyapply dpl 0x80d00000; " \
518 "run distro_bootcmd;run sd_bootcmd; " \
519 "env exists secureboot && esbc_halt;"
520
521
522#define IFC_NOR_BOOTCOMMAND \
523 "env exists mcinitcmd && env exists secureboot "\
524 "&& esbc_validate 0x580780000; env exists mcinitcmd "\
525 "&& fsl_mc lazyapply dpl 0x580d00000;" \
526 "run distro_bootcmd;run nor_bootcmd; " \
527 "env exists secureboot && esbc_halt;"
528#else
529#undef CONFIG_BOOTCOMMAND
530#ifdef CONFIG_QSPI_BOOT
531
532#define CONFIG_BOOTCOMMAND \
533 "env exists mcinitcmd && env exists secureboot "\
534 "&& esbc_validate 0x20780000; " \
535 "env exists mcinitcmd && " \
536 "fsl_mc lazyapply dpl 0x20d00000; " \
537 "run distro_bootcmd;run qspi_bootcmd; " \
538 "env exists secureboot && esbc_halt;"
539#elif defined(CONFIG_SD_BOOT)
540
541#define CONFIG_BOOTCOMMAND \
542 "env exists mcinitcmd && env exists secureboot "\
543 "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
544 "&& esbc_validate $load_addr; " \
545 "env exists mcinitcmd && run mcinitcmd " \
546 "&& mmc read 0x88000000 0x6800 0x800 " \
547 "&& fsl_mc lazyapply dpl 0x88000000; " \
548 "run distro_bootcmd;run sd_bootcmd; " \
549 "env exists secureboot && esbc_halt;"
550#else
551
552#define CONFIG_BOOTCOMMAND \
553 "env exists mcinitcmd && env exists secureboot "\
554 "&& esbc_validate 0x580780000; env exists mcinitcmd "\
555 "&& fsl_mc lazyapply dpl 0x580d00000;" \
556 "run distro_bootcmd;run nor_bootcmd; " \
557 "env exists secureboot && esbc_halt;"
558#endif
559#endif
560
561
562#ifdef CONFIG_FSL_MC_ENET
563#ifdef CONFIG_QSPI_BOOT
564#define CONFIG_CORTINA_FW_ADDR 0x20980000
565#else
566#define CONFIG_CORTINA_FW_ADDR 0x580980000
567#endif
568#define CONFIG_CORTINA_FW_LENGTH 0x40000
569
570#define CORTINA_PHY_ADDR1 0x10
571#define CORTINA_PHY_ADDR2 0x11
572#define CORTINA_PHY_ADDR3 0x12
573#define CORTINA_PHY_ADDR4 0x13
574#define AQ_PHY_ADDR1 0x00
575#define AQ_PHY_ADDR2 0x01
576#define AQ_PHY_ADDR3 0x02
577#define AQ_PHY_ADDR4 0x03
578#define AQR405_IRQ_MASK 0x36
579
580#define CONFIG_ETHPRIME "DPMAC1@xgmii"
581#endif
582
583#include <asm/fsl_secure_boot.h>
584
585#endif
586
