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2
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4
5
6#ifndef __LX2_COMMON_H
7#define __LX2_COMMON_H
8
9#include <asm/arch/stream_id_lsch3.h>
10#include <asm/arch/config.h>
11#include <asm/arch/soc.h>
12
13#define CONFIG_REMAKE_ELF
14#define CONFIG_FSL_LAYERSCAPE
15#define CONFIG_GICV3
16#define CONFIG_FSL_TZPC_BP147
17#define CONFIG_FSL_MEMAC
18
19#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
20#define CONFIG_SYS_FLASH_BASE 0x20000000
21
22#define CONFIG_SKIP_LOWLEVEL_INIT
23#define CONFIG_BOARD_EARLY_INIT_F 1
24
25
26#define CONFIG_FSL_DDR_INTERACTIVE
27#define CONFIG_SYS_FSL_DDR_INTLV_256B
28#define CONFIG_VERY_BIG_RAM
29#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
30#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
31#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
32#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
33#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
34#define CONFIG_DDR_SPD
35#define CONFIG_DDR_ECC
36#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
37#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
38#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
39#define SPD_EEPROM_ADDRESS1 0x51
40#define SPD_EEPROM_ADDRESS2 0x52
41#define SPD_EEPROM_ADDRESS3 0x53
42#define SPD_EEPROM_ADDRESS4 0x54
43#define SPD_EEPROM_ADDRESS5 0x55
44#define SPD_EEPROM_ADDRESS6 0x56
45#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
46#define CONFIG_SYS_SPD_BUS_NUM 0
47#define CONFIG_DIMM_SLOTS_PER_CTLR 2
48#define CONFIG_CHIP_SELECTS_PER_CTRL 4
49#define CONFIG_FSL_DDR_BIST
50#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
51
52
53#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
54
55
56#define CPU_RELEASE_ADDR secondary_boot_func
57
58
59
60
61
62
63
64#define COUNTER_FREQUENCY 25000000
65
66
67#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
68
69
70#define CONFIG_PL01X_SERIAL
71#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
72#define CONFIG_SYS_SERIAL0 0x21c0000
73#define CONFIG_SYS_SERIAL1 0x21d0000
74#define CONFIG_SYS_SERIAL2 0x21e0000
75#define CONFIG_SYS_SERIAL3 0x21f0000
76
77#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
78 (void *)CONFIG_SYS_SERIAL1, \
79 (void *)CONFIG_SYS_SERIAL2, \
80 (void *)CONFIG_SYS_SERIAL3 }
81#define CONFIG_BAUDRATE 115200
82#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
83
84
85#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
86#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
87#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
88#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
89#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
90
91
92
93
94#define CONFIG_RESET_PHY_R
95
96
97
98
99
100
101
102#ifdef CONFIG_FSL_MC_ENET
103#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
104#endif
105
106
107#define I2C_MUX_PCA_ADDR_PRI 0x77
108#define I2C_MUX_CH_DEFAULT 0x8
109
110
111#define RTC
112#define CONFIG_SYS_I2C_RTC_ADDR 0x51
113
114
115#define CONFIG_ID_EEPROM
116#define CONFIG_SYS_I2C_EEPROM_NXID
117#define CONFIG_SYS_EEPROM_BUS_NUM 0
118#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
119#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
120#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
121#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
122
123
124#define CONFIG_FSL_QIXIS
125#define CONFIG_QIXIS_I2C_ACCESS
126#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
127
128
129#ifdef CONFIG_PCI
130#define CONFIG_SYS_PCI_64BIT
131#define CONFIG_PCI_SCAN_SHOW
132#endif
133
134
135#ifdef CONFIG_MMC
136#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
137#endif
138
139
140
141#ifdef CONFIG_SCSI
142#define CONFIG_SCSI_AHCI_PLAT
143#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
144#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
145#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
146#define CONFIG_SYS_SCSI_MAX_LUN 1
147#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
148 CONFIG_SYS_SCSI_MAX_LUN)
149#endif
150
151
152#ifdef CONFIG_USB
153#define CONFIG_HAS_FSL_XHCI_USB
154#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
155#endif
156
157
158#ifdef CONFIG_NXP_FSPI
159#define NXP_FSPI_FLASH_SIZE SZ_64M
160#define NXP_FSPI_FLASH_NUM 1
161#endif
162
163#ifndef __ASSEMBLY__
164unsigned long get_board_sys_clk(void);
165unsigned long get_board_ddr_clk(void);
166#endif
167
168#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
169#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
170#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
171
172#define CONFIG_HWCONFIG
173#define HWCONFIG_BUFFER_SIZE 128
174
175#define CONFIG_SYS_MMC_ENV_DEV 0
176
177
178#define CONFIG_ENV_OVERWRITE
179
180
181#define CONFIG_SYS_CBSIZE 512
182#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
183 sizeof(CONFIG_SYS_PROMPT) + 16)
184#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
185#define CONFIG_SYS_MAXARGS 64
186
187#define CONFIG_SYS_BOOTM_LEN (64 << 20)
188
189
190#define XSPI_MC_INIT_CMD \
191 "env exists secureboot && " \
192 "esbc_validate 0x20700000 && " \
193 "esbc_validate 0x20740000 ;" \
194 "fsl_mc start mc 0x20a00000 0x20e00000\0"
195
196#define SD_MC_INIT_CMD \
197 "mmc read 0x80a00000 0x5000 0x1200;" \
198 "mmc read 0x80e00000 0x7000 0x800;" \
199 "env exists secureboot && " \
200 "mmc read 0x80700000 0x3800 0x10 && " \
201 "mmc read 0x80740000 0x3A00 0x10 && " \
202 "esbc_validate 0x80700000 && " \
203 "esbc_validate 0x80740000 ;" \
204 "fsl_mc start mc 0x80a00000 0x80e00000\0"
205
206#define EXTRA_ENV_SETTINGS \
207 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
208 "ramdisk_addr=0x800000\0" \
209 "ramdisk_size=0x2000000\0" \
210 "fdt_high=0xa0000000\0" \
211 "initrd_high=0xffffffffffffffff\0" \
212 "fdt_addr=0x64f00000\0" \
213 "kernel_start=0x1000000\0" \
214 "kernelheader_start=0x7C0000\0" \
215 "scriptaddr=0x80000000\0" \
216 "scripthdraddr=0x80080000\0" \
217 "fdtheader_addr_r=0x80100000\0" \
218 "kernelheader_addr_r=0x80200000\0" \
219 "kernel_addr_r=0x81000000\0" \
220 "kernelheader_size=0x40000\0" \
221 "fdt_addr_r=0x90000000\0" \
222 "load_addr=0xa0000000\0" \
223 "kernel_size=0x2800000\0" \
224 "kernel_addr_sd=0x8000\0" \
225 "kernelhdr_addr_sd=0x3E00\0" \
226 "kernel_size_sd=0x1d000\0" \
227 "kernelhdr_size_sd=0x10\0" \
228 "console=ttyAMA0,38400n8\0" \
229 BOOTENV \
230 "mcmemsize=0x70000000\0" \
231 XSPI_MC_INIT_CMD \
232 "boot_scripts=lx2160ardb_boot.scr\0" \
233 "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \
234 "scan_dev_for_boot_part=" \
235 "part list ${devtype} ${devnum} devplist; " \
236 "env exists devplist || setenv devplist 1; " \
237 "for distro_bootpart in ${devplist}; do " \
238 "if fstype ${devtype} " \
239 "${devnum}:${distro_bootpart} " \
240 "bootfstype; then " \
241 "run scan_dev_for_boot; " \
242 "fi; " \
243 "done\0" \
244 "boot_a_script=" \
245 "load ${devtype} ${devnum}:${distro_bootpart} " \
246 "${scriptaddr} ${prefix}${script}; " \
247 "env exists secureboot && load ${devtype} " \
248 "${devnum}:${distro_bootpart} " \
249 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
250 "&& esbc_validate ${scripthdraddr};" \
251 "source ${scriptaddr}\0"
252
253#define XSPI_NOR_BOOTCOMMAND \
254 "env exists mcinitcmd && env exists secureboot "\
255 "&& esbc_validate 0x20780000; " \
256 "env exists mcinitcmd && " \
257 "fsl_mc lazyapply dpl 0x20d00000; " \
258 "run distro_bootcmd;run xspi_bootcmd; " \
259 "env exists secureboot && esbc_halt;"
260
261#define SD_BOOTCOMMAND \
262 "env exists mcinitcmd && mmcinfo; " \
263 "mmc read 0x80d00000 0x6800 0x800; " \
264 "env exists mcinitcmd && env exists secureboot " \
265 " && mmc read 0x80780000 0x3C00 0x10 " \
266 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
267 "&& fsl_mc lazyapply dpl 0x80d00000;" \
268 "run distro_bootcmd;run sd_bootcmd;" \
269 "env exists secureboot && esbc_halt;"
270
271#define BOOT_TARGET_DEVICES(func) \
272 func(USB, usb, 0) \
273 func(MMC, mmc, 0) \
274 func(SCSI, scsi, 0)
275#include <config_distro_bootcmd.h>
276
277#endif
278
