1#ifndef __CONFIG_H 2#define __CONFIG_H 3 4#define CONFIG_CPU_SH7751 1 5#define __LITTLE_ENDIAN__ 1 6 7#define CONFIG_DISPLAY_BOARDINFO 8 9/* SCIF */ 10#define CONFIG_CONS_SCIF1 1 11 12#define CONFIG_ENV_OVERWRITE 1 13 14/* SDRAM */ 15#define CONFIG_SYS_SDRAM_BASE 0x8C000000 16#define CONFIG_SYS_SDRAM_SIZE 0x04000000 17 18#define CONFIG_SYS_PBSIZE 256 19 20#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 21#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 22 23#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 24/* Address of u-boot image in Flash */ 25#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 26#define CONFIG_SYS_MONITOR_LEN (256 * 1024) 27/* Size of DRAM reserved for malloc() use */ 28#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 29#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 30 31/* 32 * NOR Flash ( Spantion S29GL256P ) 33 */ 34#define CONFIG_SYS_FLASH_BASE (0xA0000000) 35#define CONFIG_SYS_MAX_FLASH_BANKS (1) 36#define CONFIG_SYS_MAX_FLASH_SECT 256 37#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 38 39/* 40 * SuperH Clock setting 41 */ 42#define CONFIG_SYS_CLK_FREQ 60000000 43#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 44#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ 45 46/* 47 * IDE support 48 */ 49#define CONFIG_IDE_RESET 1 50#define CONFIG_SYS_PIO_MODE 1 51#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 52#define CONFIG_SYS_IDE_MAXDEVICE 1 53#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 54#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 55#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 56#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ 57#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 58#define CONFIG_IDE_SWAP_IO 59 60/* 61 * SuperH PCI Bridge Configration 62 */ 63#define CONFIG_SH7751_PCI 64 65#endif /* __CONFIG_H */ 66