LXR uboot/include/configs/socrates.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2008
   4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   5 *
   6 * Wolfgang Denk <wd@denx.de>
   7 * Copyright 2004 Freescale Semiconductor.
   8 * (C) Copyright 2002,2003 Motorola,Inc.
   9 * Xianghua Xiao <X.Xiao@motorola.com>
  10 */
  11
  12/*
  13 * Socrates
  14 */
  15
  16#ifndef __CONFIG_H
  17#define __CONFIG_H
  18
  19/* High Level Configuration Options */
  20#define CONFIG_SOCRATES         1
  21
  22/*
  23 * Only possible on E500 Version 2 or newer cores.
  24 */
  25#define CONFIG_ENABLE_36BIT_PHYS        1
  26
  27/*
  28 * sysclk for MPC85xx
  29 *
  30 * Two valid values are:
  31 *    33000000
  32 *    66000000
  33 *
  34 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  35 * is likely the desired value here, so that is now the default.
  36 * The board, however, can run at 66MHz.  In any event, this value
  37 * must match the settings of some switches.  Details can be found
  38 * in the README.mpc85xxads.
  39 */
  40
  41#ifndef CONFIG_SYS_CLK_FREQ
  42#define CONFIG_SYS_CLK_FREQ     66666666
  43#endif
  44
  45/*
  46 * These can be toggled for performance analysis, otherwise use default.
  47 */
  48#define CONFIG_L2_CACHE                 /* toggle L2 cache              */
  49#define CONFIG_BTB                      /* toggle branch predition      */
  50
  51#define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions      */
  52
  53#undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time      */
  54#define CONFIG_SYS_MEMTEST_START        0x00400000
  55#define CONFIG_SYS_MEMTEST_END          0x00C00000
  56
  57#define CONFIG_SYS_CCSRBAR              0xE0000000
  58#define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  59
  60/* DDR Setup */
  61#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  62#define CONFIG_DDR_SPD
  63
  64#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER        /* DDR controller or DMA? */
  65#define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  66
  67#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  68#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  69#define CONFIG_VERY_BIG_RAM
  70
  71#define CONFIG_DIMM_SLOTS_PER_CTLR      1
  72#define CONFIG_CHIP_SELECTS_PER_CTRL    2
  73
  74/* I2C addresses of SPD EEPROMs */
  75#define SPD_EEPROM_ADDRESS      0x50    /* CTLR 0 DIMM 0 */
  76
  77#define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
  78
  79/* Hardcoded values, to use instead of SPD */
  80#define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
  81#define CONFIG_SYS_DDR_CS0_CONFIG               0x80010102
  82#define CONFIG_SYS_DDR_TIMING_0         0x00260802
  83#define CONFIG_SYS_DDR_TIMING_1         0x3935D322
  84#define CONFIG_SYS_DDR_TIMING_2         0x14904CC8
  85#define CONFIG_SYS_DDR_MODE                     0x00480432
  86#define CONFIG_SYS_DDR_INTERVAL         0x030C0100
  87#define CONFIG_SYS_DDR_CONFIG_2         0x04400000
  88#define CONFIG_SYS_DDR_CONFIG                   0xC3008000
  89#define CONFIG_SYS_DDR_CLK_CONTROL              0x03800000
  90#define CONFIG_SYS_SDRAM_SIZE                   256 /* in Megs */
  91
  92/*
  93 * Flash on the LocalBus
  94 */
  95#define CONFIG_SYS_LBC_CACHE_BASE       0xf0000000      /* Localbus cacheable    */
  96
  97#define CONFIG_SYS_FLASH_QUIET_TEST
  98#define CONFIG_SYS_FLASH0               0xFE000000
  99#define CONFIG_SYS_FLASH1               0xFC000000
 100#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 101
 102#define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH1       /* Localbus flash start */
 103#define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH     */
 104
 105#define CONFIG_SYS_BR0_PRELIM           0xfe001001      /* port size 16bit      */
 106#define CONFIG_SYS_OR0_PRELIM           0xfe000030      /* 32MB Flash           */
 107#define CONFIG_SYS_BR1_PRELIM           0xfc001001      /* port size 16bit      */
 108#define CONFIG_SYS_OR1_PRELIM           0xfe000030      /* 32MB Flash           */
 109
 110#define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks      */
 111#define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per device   */
 112#undef  CONFIG_SYS_FLASH_CHECKSUM
 113#define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms)     */
 114#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms)     */
 115
 116#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
 117
 118#define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg     */
 119#define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg          */
 120#define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 121#define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer presc.*/
 122
 123#define CONFIG_SYS_INIT_RAM_LOCK        1
 124#define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address  */
 125#define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size used area in RAM*/
 126
 127#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 128#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 129
 130#define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384KiB for Mon */
 131#define CONFIG_SYS_MALLOC_LEN           (4 << 20)       /* Reserve 4 MB for malloc */
 132
 133/* FPGA and NAND */
 134#define CONFIG_SYS_FPGA_BASE            0xc0000000
 135#define CONFIG_SYS_FPGA_SIZE            0x00100000      /* 1 MB         */
 136#define CONFIG_SYS_HMI_BASE             0xc0010000
 137#define CONFIG_SYS_BR3_PRELIM           0xc0001881      /* UPMA, 32-bit */
 138#define CONFIG_SYS_OR3_PRELIM           0xfff00000      /* 1 MB         */
 139
 140#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_FPGA_BASE + 0x70)
 141#define CONFIG_SYS_MAX_NAND_DEVICE      1
 142
 143/* LIME GDC */
 144#define CONFIG_SYS_LIME_BASE            0xc8000000
 145#define CONFIG_SYS_LIME_SIZE            0x04000000      /* 64 MB        */
 146#define CONFIG_SYS_BR2_PRELIM           0xc80018a1      /* UPMB, 32-bit */
 147#define CONFIG_SYS_OR2_PRELIM           0xfc000000      /* 64 MB        */
 148
 149#define CONFIG_SYS_SPD_BUS_NUM 0
 150
 151#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 152
 153/*
 154 * General PCI
 155 * Memory space is mapped 1-1.
 156 */
 157
 158/* PCI is clocked by the external source at 33 MHz */
 159#define CONFIG_PCI_CLK_FREQ     33000000
 160#define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 161#define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 162#define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M                 */
 163#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
 164#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
 165#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000      /* 16M                  */
 166
 167#define CONFIG_TSEC1    1
 168#define CONFIG_TSEC1_NAME       "TSEC0"
 169#define CONFIG_TSEC3    1
 170#define CONFIG_TSEC3_NAME       "TSEC1"
 171#undef CONFIG_MPC85XX_FEC
 172
 173#define TSEC1_PHY_ADDR          0
 174#define TSEC3_PHY_ADDR          1
 175
 176#define TSEC1_PHYIDX            0
 177#define TSEC3_PHYIDX            0
 178#define TSEC1_FLAGS             TSEC_GIGABIT
 179#define TSEC3_FLAGS             TSEC_GIGABIT
 180
 181/* Options are: TSEC[0,1] */
 182#define CONFIG_ETHPRIME         "TSEC0"
 183
 184#define CONFIG_HAS_ETH0
 185#define CONFIG_HAS_ETH1
 186
 187/*
 188 * Environment
 189 */
 190
 191#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 192#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 193
 194#define CONFIG_TIMESTAMP                /* Print image info with ts     */
 195
 196/*
 197 * BOOTP options
 198 */
 199#define CONFIG_BOOTP_BOOTFILESIZE
 200
 201#undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 202
 203/*
 204 * Miscellaneous configurable options
 205 */
 206#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address         */
 207
 208/*
 209 * For booting Linux, the board info and command line data
 210 * have to be in the first 8 MB of memory, since this is
 211 * the maximum mapped by the Linux kernel during initialization.
 212 */
 213#define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
 214
 215#if defined(CONFIG_CMD_KGDB)
 216#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
 217#endif
 218
 219#define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
 220
 221#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 222        "netdev=eth0\0"                                                 \
 223        "consdev=ttyS0\0"                                               \
 224        "uboot_file=/home/tftp/syscon3/u-boot.bin\0"                    \
 225        "bootfile=/home/tftp/syscon3/uImage\0"                          \
 226        "fdt_file=/home/tftp/syscon3/socrates.dtb\0"                    \
 227        "initrd_file=/home/tftp/syscon3/uinitrd.gz\0"                   \
 228        "uboot_addr=FFF60000\0"                                         \
 229        "kernel_addr=FE000000\0"                                        \
 230        "fdt_addr=FE1E0000\0"                                           \
 231        "ramdisk_addr=FE200000\0"                                       \
 232        "fdt_addr_r=B00000\0"                                           \
 233        "kernel_addr_r=200000\0"                                        \
 234        "ramdisk_addr_r=400000\0"                                       \
 235        "rootpath=/opt/eldk/ppc_85xxDP\0"                               \
 236        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 237        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 238                "nfsroot=$serverip:$rootpath\0"                         \
 239        "addcons=setenv bootargs $bootargs "                            \
 240                "console=$consdev,$baudrate\0"                          \
 241        "addip=setenv bootargs $bootargs "                              \
 242                "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 243                ":$hostname:$netdev:off panic=1\0"                      \
 244        "boot_nor=run ramargs addcons;"                                 \
 245                "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 246        "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
 247                "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 248                "run nfsargs addip addcons;"                            \
 249                "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 250        "update_uboot=tftp 100000 ${uboot_file};"                       \
 251                "protect off fff60000 ffffffff;"                        \
 252                "era fff60000 ffffffff;"                                \
 253                "cp.b 100000 fff60000 ${filesize};"                     \
 254                "setenv filesize;saveenv\0"                             \
 255        "update_kernel=tftp 100000 ${bootfile};"                        \
 256                "era fe000000 fe1dffff;"                                \
 257                "cp.b 100000 fe000000 ${filesize};"                     \
 258                "setenv filesize;saveenv\0"                             \
 259        "update_fdt=tftp 100000 ${fdt_file};"                           \
 260                "era fe1e0000 fe1fffff;"                                \
 261                "cp.b 100000 fe1e0000 ${filesize};"                     \
 262                "setenv filesize;saveenv\0"                             \
 263        "update_initrd=tftp 100000 ${initrd_file};"                     \
 264                "era fe200000 fe9fffff;"                                \
 265                "cp.b 100000 fe200000 ${filesize};"                     \
 266                "setenv filesize;saveenv\0"                             \
 267        "clean_data=era fea00000 fff5ffff\0"                            \
 268        "usbargs=setenv bootargs root=/dev/sda1 rw\0"                   \
 269        "load_usb=usb start;"                                           \
 270                "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"      \
 271        "boot_usb=run load_usb usbargs addcons;"                        \
 272                "bootm ${kernel_addr_r} - ${fdt_addr};"                 \
 273                "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 274        ""
 275#define CONFIG_BOOTCOMMAND      "run boot_nor"
 276
 277/* pass open firmware flat tree */
 278
 279/* USB support */
 280#define CONFIG_USB_OHCI_NEW             1
 281#define CONFIG_PCI_OHCI                 1
 282#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 283#define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 284#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 285
 286#endif  /* __CONFIG_H */
 287