1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6/* 7 * Corenet DS style board configuration file 8 */ 9#ifndef __T4QDS_H 10#define __T4QDS_H 11 12/* High Level Configuration Options */ 13#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 14 15#ifndef CONFIG_RESET_VECTOR_ADDRESS 16#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 17#endif 18 19#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 20#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 21#define CONFIG_PCIE1 /* PCIE controller 1 */ 22#define CONFIG_PCIE2 /* PCIE controller 2 */ 23#define CONFIG_PCIE3 /* PCIE controller 3 */ 24#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 25#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 26 27#define CONFIG_SYS_SRIO 28#define CONFIG_SRIO1 /* SRIO port 1 */ 29#define CONFIG_SRIO2 /* SRIO port 2 */ 30 31#define CONFIG_ENV_OVERWRITE 32 33/* 34 * These can be toggled for performance analysis, otherwise use default. 35 */ 36#define CONFIG_SYS_CACHE_STASHING 37#define CONFIG_BTB /* toggle branch predition */ 38#ifdef CONFIG_DDR_ECC 39#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 40#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 41#endif 42 43#define CONFIG_ENABLE_36BIT_PHYS 44 45#define CONFIG_ADDR_MAP 46#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 47 48#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 49#define CONFIG_SYS_MEMTEST_END 0x00400000 50 51/* 52 * Config the L3 Cache as L3 SRAM 53 */ 54#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 55#define CONFIG_SYS_L3_SIZE (512 << 10) 56#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 57#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 58#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 59#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 60#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 61 62#define CONFIG_SYS_DCSRBAR 0xf0000000 63#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 64 65/* 66 * DDR Setup 67 */ 68#define CONFIG_VERY_BIG_RAM 69#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 70#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 71 72#define CONFIG_DIMM_SLOTS_PER_CTLR 2 73#define CONFIG_CHIP_SELECTS_PER_CTRL 4 74 75#define CONFIG_DDR_SPD 76 77/* 78 * IFC Definitions 79 */ 80#define CONFIG_SYS_FLASH_BASE 0xe0000000 81#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 82 83#ifdef CONFIG_SPL_BUILD 84#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 85#else 86#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 87#endif 88 89#define CONFIG_HWCONFIG 90 91/* define to use L1 as initial stack */ 92#define CONFIG_L1_INIT_RAM 93#define CONFIG_SYS_INIT_RAM_LOCK 94#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 95#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 96#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 97/* The assembler doesn't like typecast */ 98#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 99 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 100 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 101#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 102 103#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 104 GENERATED_GBL_DATA_SIZE) 105#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 106 107#define CONFIG_SYS_MONITOR_LEN (768 * 1024) 108#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 109 110/* Serial Port - controlled on board with jumper J8 111 * open - index 2 112 * shorted - index 1 113 */ 114#define CONFIG_SYS_NS16550_SERIAL 115#define CONFIG_SYS_NS16550_REG_SIZE 1 116#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 117 118#define CONFIG_SYS_BAUDRATE_TABLE \ 119 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 120 121#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 122#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 123#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 124#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 125 126/* I2C */ 127#define CONFIG_SYS_I2C 128#define CONFIG_SYS_I2C_FSL 129#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 130#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 131#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 132#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 133 134/* 135 * RapidIO 136 */ 137#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 138#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 139#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 140 141#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 142#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 143#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 144 145/* 146 * General PCI 147 * Memory space is mapped 1-1, but I/O space must start from 0. 148 */ 149 150/* controller 1, direct to uli, tgtid 3, Base address 20000 */ 151#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 152#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 153#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 154#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 155#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 156#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 157#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 158#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 159 160/* controller 2, Slot 2, tgtid 2, Base address 201000 */ 161#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 162#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 163#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 164#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 165#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 166#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 167#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 168#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 169 170/* controller 3, Slot 1, tgtid 1, Base address 202000 */ 171#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 172#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 173#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 174#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 175#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 176#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 177#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 178#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 179 180/* controller 4, Base address 203000 */ 181#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 182#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 183#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 184#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 185#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 186#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 187 188#ifdef CONFIG_PCI 189#define CONFIG_PCI_INDIRECT_BRIDGE 190 191#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 192#endif /* CONFIG_PCI */ 193 194/* SATA */ 195#ifdef CONFIG_FSL_SATA_V2 196#define CONFIG_SYS_SATA_MAX_DEVICE 2 197#define CONFIG_SATA1 198#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 199#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 200#define CONFIG_SATA2 201#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 202#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 203 204#define CONFIG_LBA48 205#endif 206 207#ifdef CONFIG_FMAN_ENET 208#define CONFIG_ETHPRIME "FM1@DTSEC1" 209#endif 210 211/* 212 * Environment 213 */ 214#define CONFIG_LOADS_ECHO /* echo on for serial download */ 215#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 216 217/* 218 * Command line configuration. 219 */ 220 221/* 222 * Miscellaneous configurable options 223 */ 224#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 225 226/* 227 * For booting Linux, the board info and command line data 228 * have to be in the first 64 MB of memory, since this is 229 * the maximum mapped by the Linux kernel during initialization. 230 */ 231#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 232#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 233 234#ifdef CONFIG_CMD_KGDB 235#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 236#endif 237 238/* 239 * Environment Configuration 240 */ 241#define CONFIG_ROOTPATH "/opt/nfsroot" 242#define CONFIG_BOOTFILE "uImage" 243#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 244 245/* default location for tftp and bootm */ 246#define CONFIG_LOADADDR 1000000 247 248#define CONFIG_HVBOOT \ 249 "setenv bootargs config-addr=0x60000000; " \ 250 "bootm 0x01000000 - 0x00f00000" 251 252#endif /* __CONFIG_H */ 253