LXR uboot/include/configs/vexpress

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Configuration for Versatile Express. Parts were derived from other ARM
   4 *   configurations.
   5 */
   6
   7#ifndef __VEXPRESS_AEMV8A_H
   8#define __VEXPRESS_AEMV8A_H
   9
  10#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  11#ifndef CONFIG_SEMIHOSTING
  12#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
  13#endif
  14#endif
  15
  16#define CONFIG_REMAKE_ELF
  17
  18/* Link Definitions */
  19#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  20/* ATF loads u-boot here for BASE_FVP model */
  21#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
  22#elif CONFIG_TARGET_VEXPRESS64_JUNO
  23#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
  24#endif
  25
  26#define CONFIG_SYS_BOOTM_LEN (64 << 20)      /* Increase max gunzip size */
  27
  28/* CS register bases for the original memory map. */
  29#define V2M_PA_CS0                      0x00000000
  30#define V2M_PA_CS1                      0x14000000
  31#define V2M_PA_CS2                      0x18000000
  32#define V2M_PA_CS3                      0x1c000000
  33#define V2M_PA_CS4                      0x0c000000
  34#define V2M_PA_CS5                      0x10000000
  35
  36#define V2M_PERIPH_OFFSET(x)            (x << 16)
  37#define V2M_SYSREGS                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
  38#define V2M_SYSCTL                      (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
  39#define V2M_SERIAL_BUS_PCI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
  40
  41#define V2M_BASE                        0x80000000
  42
  43/* Common peripherals relative to CS7. */
  44#define V2M_AACI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
  45#define V2M_MMCI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
  46#define V2M_KMI0                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
  47#define V2M_KMI1                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
  48
  49#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  50#define V2M_UART0                       0x7ff80000
  51#define V2M_UART1                       0x7ff70000
  52#else /* Not Juno */
  53#define V2M_UART0                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
  54#define V2M_UART1                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
  55#define V2M_UART2                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
  56#define V2M_UART3                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
  57#endif
  58
  59#define V2M_WDT                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
  60
  61#define V2M_TIMER01                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
  62#define V2M_TIMER23                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
  63
  64#define V2M_SERIAL_BUS_DVI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
  65#define V2M_RTC                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
  66
  67#define V2M_CF                          (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
  68
  69#define V2M_CLCD                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
  70
  71/* System register offsets. */
  72#define V2M_SYS_CFGDATA                 (V2M_SYSREGS + 0x0a0)
  73#define V2M_SYS_CFGCTRL                 (V2M_SYSREGS + 0x0a4)
  74#define V2M_SYS_CFGSTAT                 (V2M_SYSREGS + 0x0a8)
  75
  76/* Generic Timer Definitions */
  77#define COUNTER_FREQUENCY               (0x1800000)     /* 24MHz */
  78
  79/* Generic Interrupt Controller Definitions */
  80#ifdef CONFIG_GICV3
  81#define GICD_BASE                       (0x2f000000)
  82#define GICR_BASE                       (0x2f100000)
  83#else
  84
  85#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  86#define GICD_BASE                       (0x2f000000)
  87#define GICC_BASE                       (0x2c000000)
  88#elif CONFIG_TARGET_VEXPRESS64_JUNO
  89#define GICD_BASE                       (0x2C010000)
  90#define GICC_BASE                       (0x2C02f000)
  91#endif
  92#endif /* !CONFIG_GICV3 */
  93
  94/* Size of malloc() pool */
  95#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (8 << 20))
  96
  97#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
  98/* The Vexpress64 simulators use SMSC91C111 */
  99#define CONFIG_SMC91111                 1
 100#define CONFIG_SMC91111_BASE            (0x01A000000)
 101#endif
 102
 103/* PL011 Serial Configuration */
 104#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 105#define CONFIG_PL011_CLOCK              7273800
 106#else
 107#define CONFIG_PL011_CLOCK              24000000
 108#endif
 109
 110/* BOOTP options */
 111#define CONFIG_BOOTP_BOOTFILESIZE
 112
 113/* Miscellaneous configurable options */
 114#define CONFIG_SYS_LOAD_ADDR            (V2M_BASE + 0x10000000)
 115
 116/* Physical Memory Map */
 117#define PHYS_SDRAM_1                    (V2M_BASE)      /* SDRAM Bank #1 */
 118/* Top 16MB reserved for secure world use */
 119#define DRAM_SEC_SIZE           0x01000000
 120#define PHYS_SDRAM_1_SIZE       0x80000000 - DRAM_SEC_SIZE
 121#define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM_1
 122
 123#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 124#define PHYS_SDRAM_2                    (0x880000000)
 125#define PHYS_SDRAM_2_SIZE               0x180000000
 126#endif
 127
 128/* Enable memtest */
 129#define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
 130#define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
 131
 132/* Initial environment variables */
 133#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 134/*
 135 * Defines where the kernel and FDT exist in NOR flash and where it will
 136 * be copied into DRAM
 137 */
 138#define CONFIG_EXTRA_ENV_SETTINGS       \
 139                                "kernel_name=norkern\0" \
 140                                "kernel_alt_name=Image\0"       \
 141                                "kernel_addr=0x80080000\0" \
 142                                "initrd_name=ramdisk.img\0"     \
 143                                "initrd_addr=0x84000000\0"      \
 144                                "fdtfile=board.dtb\0" \
 145                                "fdt_alt_name=juno\0" \
 146                                "fdt_addr=0x83000000\0" \
 147                                "fdt_high=0xffffffffffffffff\0" \
 148                                "initrd_high=0xffffffffffffffff\0" \
 149
 150/* Copy the kernel and FDT to DRAM memory and boot */
 151#define CONFIG_BOOTCOMMAND      "afs load ${kernel_name} ${kernel_addr} ; " \
 152                                "if test $? -eq 1; then "\
 153                                "  echo Loading ${kernel_alt_name} instead of "\
 154                                "${kernel_name}; "\
 155                                "  afs load ${kernel_alt_name} ${kernel_addr};"\
 156                                "fi ; "\
 157                                "afs load  ${fdtfile} ${fdt_addr} ; " \
 158                                "if test $? -eq 1; then "\
 159                                "  echo Loading ${fdt_alt_name} instead of "\
 160                                "${fdtfile}; "\
 161                                "  afs load ${fdt_alt_name} ${fdt_addr}; "\
 162                                "fi ; "\
 163                                "fdt addr ${fdt_addr}; fdt resize; " \
 164                                "if afs load  ${initrd_name} ${initrd_addr} ; "\
 165                                "then "\
 166                                "  setenv initrd_param ${initrd_addr}; "\
 167                                "  else setenv initrd_param -; "\
 168                                "fi ; " \
 169                                "booti ${kernel_addr} ${initrd_param} ${fdt_addr}"
 170
 171
 172#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
 173#define CONFIG_EXTRA_ENV_SETTINGS       \
 174                                "kernel_name=Image\0"           \
 175                                "kernel_addr=0x80080000\0"      \
 176                                "initrd_name=ramdisk.img\0"     \
 177                                "initrd_addr=0x88000000\0"      \
 178                                "fdtfile=devtree.dtb\0"         \
 179                                "fdt_addr=0x83000000\0"         \
 180                                "fdt_high=0xffffffffffffffff\0" \
 181                                "initrd_high=0xffffffffffffffff\0"
 182
 183#define CONFIG_BOOTCOMMAND      "smhload ${kernel_name} ${kernel_addr}; " \
 184                                "smhload ${fdtfile} ${fdt_addr}; " \
 185                                "smhload ${initrd_name} ${initrd_addr} "\
 186                                "initrd_end; " \
 187                                "fdt addr ${fdt_addr}; fdt resize; " \
 188                                "fdt chosen ${initrd_addr} ${initrd_end}; " \
 189                                "booti $kernel_addr - $fdt_addr"
 190
 191
 192#endif
 193
 194/* Monitor Command Prompt */
 195#define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 196#define CONFIG_SYS_MAXARGS              64      /* max command args */
 197
 198#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 199#define CONFIG_SYS_FLASH_BASE           0x08000000
 200/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
 201#define CONFIG_SYS_MAX_FLASH_SECT       259
 202/* Store environment at top of flash in the same location as blank.img */
 203/* in the Juno firmware. */
 204#else
 205#define CONFIG_SYS_FLASH_BASE           0x0C000000
 206/* 256 x 256KiB sectors */
 207#define CONFIG_SYS_MAX_FLASH_SECT       256
 208/* Store environment at top of flash */
 209#endif
 210
 211#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
 212#define CONFIG_SYS_MAX_FLASH_BANKS      1
 213
 214#define CONFIG_SYS_FLASH_EMPTY_INFO     /* flinfo indicates empty blocks */
 215#define FLASH_MAX_SECTOR_SIZE           0x00040000
 216
 217#endif /* __VEXPRESS_AEMV8A_H */
 218