LXR uboot/include/configs/x600.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
   4 * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
   5 *
   6 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
   7 */
   8
   9#ifndef __CONFIG_H
  10#define __CONFIG_H
  11
  12/*
  13 * High Level Configuration Options
  14 * (easy to change)
  15 */
  16#define CONFIG_SPEAR600                         /* SPEAr600 SoC */
  17#define CONFIG_X600                             /* on X600 board */
  18
  19#include <asm/arch/hardware.h>
  20
  21/* Timer, HZ specific defines */
  22#define CONFIG_SYS_HZ_CLOCK                     8300000
  23
  24#define CONFIG_SYS_FLASH_BASE                   0xf8000000
  25/* Reserve 8KiB for SPL */
  26#define CONFIG_SPL_PAD_TO                       8192    /* decimal for 'dd' */
  27#define CONFIG_SYS_SPL_LEN                      CONFIG_SPL_PAD_TO
  28#define CONFIG_SYS_UBOOT_BASE                   (CONFIG_SYS_FLASH_BASE + \
  29                                                 CONFIG_SYS_SPL_LEN)
  30#define CONFIG_SYS_UBOOT_START                  CONFIG_SYS_TEXT_BASE
  31#define CONFIG_SYS_MONITOR_BASE                 CONFIG_SYS_FLASH_BASE
  32#define CONFIG_SYS_MONITOR_LEN                  0x60000
  33
  34/* Serial Configuration (PL011) */
  35#define CONFIG_SYS_SERIAL0                      0xD0000000
  36#define CONFIG_SYS_SERIAL1                      0xD0080000
  37#define CONFIG_PL01x_PORTS                      { (void *)CONFIG_SYS_SERIAL0, \
  38                                                (void *)CONFIG_SYS_SERIAL1 }
  39#define CONFIG_PL011_CLOCK                      (48 * 1000 * 1000)
  40#define CONFIG_SYS_BAUDRATE_TABLE               { 9600, 19200, 38400, \
  41                                                  57600, 115200 }
  42#define CONFIG_SYS_LOADS_BAUD_CHANGE
  43
  44/* NOR FLASH config options */
  45#define CONFIG_ST_SMI
  46#define CONFIG_SYS_MAX_FLASH_BANKS              1
  47#define CONFIG_SYS_FLASH_BANK_SIZE              0x01000000
  48#define CONFIG_SYS_FLASH_ADDR_BASE              { CONFIG_SYS_FLASH_BASE }
  49#define CONFIG_SYS_MAX_FLASH_SECT               128
  50#define CONFIG_SYS_FLASH_EMPTY_INFO
  51#define CONFIG_SYS_FLASH_ERASE_TOUT             (3 * CONFIG_SYS_HZ)
  52#define CONFIG_SYS_FLASH_WRITE_TOUT             (3 * CONFIG_SYS_HZ)
  53
  54/* NAND FLASH config options */
  55#define CONFIG_NAND_FSMC
  56#define CONFIG_SYS_NAND_SELF_INIT
  57#define CONFIG_SYS_MAX_NAND_DEVICE              1
  58#define CONFIG_SYS_NAND_BASE                    CONFIG_FSMC_NAND_BASE
  59#define CONFIG_MTD_ECC_SOFT
  60#define CONFIG_SYS_FSMC_NAND_8BIT
  61#define CONFIG_SYS_NAND_ONFI_DETECTION
  62#define CONFIG_NAND_ECC_BCH
  63
  64/* UBI/UBI config options */
  65
  66/* Ethernet config options */
  67#define CONFIG_PHY_RESET_DELAY                  10000           /* in usec */
  68
  69#define CONFIG_SPEAR_GPIO
  70
  71/* I2C config options */
  72#define CONFIG_SYS_I2C
  73#define CONFIG_SYS_I2C_BASE                     0xD0200000
  74#define CONFIG_SYS_I2C_SPEED                    400000
  75#define CONFIG_SYS_I2C_SLAVE                    0x02
  76#define CONFIG_I2C_CHIPADDRESS                  0x50
  77
  78#define CONFIG_SYS_I2C_RTC_ADDR 0x68
  79
  80/* FPGA config options */
  81#define CONFIG_FPGA_COUNT       1
  82
  83/* USB EHCI options */
  84#define CONFIG_USB_EHCI_SPEAR
  85#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  86
  87/*
  88 * U-Boot Environment placing definitions.
  89 */
  90
  91/* Miscellaneous configurable options */
  92#define CONFIG_BOOT_PARAMS_ADDR                 0x00000100
  93#define CONFIG_CMDLINE_TAG
  94#define CONFIG_SETUP_MEMORY_TAGS
  95
  96#define CONFIG_SYS_MEMTEST_START                0x00800000
  97#define CONFIG_SYS_MEMTEST_END                  0x04000000
  98#define CONFIG_SYS_MALLOC_LEN                   (8 << 20)
  99#define CONFIG_SYS_LOAD_ADDR                    0x00800000
 100
 101#define CONFIG_HOSTNAME                         "x600"
 102#define CONFIG_UBI_PART                         ubi0
 103#define CONFIG_UBIFS_VOLUME                     rootfs
 104
 105#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 106        "u-boot_addr=1000000\0"                                         \
 107        "u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0"               \
 108        "load=tftp ${u-boot_addr} ${u-boot}\0"                          \
 109        "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 110                " +${filesize};"                                        \
 111                "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
 112                "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
 113                " ${filesize};"                                         \
 114                "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 115                " +${filesize}\0"                                       \
 116        "upd=run load update\0"                                         \
 117        "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0"         \
 118        "part=" __stringify(CONFIG_UBI_PART) "\0"                       \
 119        "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"                    \
 120        "load_ubifs=tftp ${kernel_addr} ${ubifs}\0"                     \
 121        "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
 122                " ${filesize}\0"                                        \
 123        "upd_ubifs=run load_ubifs update_ubifs\0"                       \
 124        "init_ubifs=nand erase.part ubi0;ubi part ${part};"             \
 125                "ubi create ${vol} 4000000\0"                           \
 126        "netdev=eth0\0"                                                 \
 127        "rootpath=/opt/eldk-4.2/arm\0"                                  \
 128        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 129                "nfsroot=${serverip}:${rootpath}\0"                     \
 130        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 131        "boot_part=0\0"                                                 \
 132        "altbootcmd=if test $boot_part -eq 0;then "                     \
 133                        "echo Switching to partition 1!;"               \
 134                        "setenv boot_part 1;"                           \
 135                "else; "                                                \
 136                        "echo Switching to partition 0!;"               \
 137                        "setenv boot_part 0;"                           \
 138                "fi;"                                                   \
 139                "saveenv;boot\0"                                        \
 140        "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} "               \
 141                "root=ubi0:rootfs rootfstype=ubifs\0"                   \
 142        "kernel=" CONFIG_HOSTNAME "/uImage\0"           \
 143        "kernel_fs=/boot/uImage \0"                                     \
 144        "kernel_addr=1000000\0"                                         \
 145        "dtb=" CONFIG_HOSTNAME "/"                              \
 146                CONFIG_HOSTNAME ".dtb\0"                        \
 147        "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0"                \
 148        "dtb_addr=1800000\0"                                            \
 149        "load_kernel=tftp ${kernel_addr} ${kernel}\0"                   \
 150        "load_dtb=tftp ${dtb_addr} ${dtb}\0"                            \
 151        "addip=setenv bootargs ${bootargs} "                            \
 152                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 153                ":${hostname}:${netdev}:off panic=1\0"                  \
 154        "addcon=setenv bootargs ${bootargs} console=ttyAMA0,"           \
 155                "${baudrate}\0"                                         \
 156        "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 157        "net_nfs=run load_dtb load_kernel; "                            \
 158                "run nfsargs addip addcon addmtd addmisc;"              \
 159                "bootm ${kernel_addr} - ${dtb_addr}\0"                  \
 160        "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"                                    \
 161        "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"                                \
 162        "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"         \
 163                " addcon addmisc addmtd;"                               \
 164                "bootm ${kernel_addr} - ${dtb_addr}\0"                  \
 165        "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0"  \
 166        "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"             \
 167                "ubifsload ${dtb_addr} ${dtb_fs};\0"                    \
 168        "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
 169                "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0"   \
 170        "bootcmd=run nand_ubifs\0"                                      \
 171        "\0"
 172
 173/* Physical Memory Map */
 174#define PHYS_SDRAM_1                            0x00000000
 175#define PHYS_SDRAM_1_MAXSIZE                    0x40000000
 176
 177#define CONFIG_SYS_SDRAM_BASE                   PHYS_SDRAM_1
 178#define CONFIG_SRAM_BASE                        0xd2800000
 179/* Preserve the last 2 lwords for the boot-counter */
 180#define CONFIG_SRAM_SIZE                        ((8 << 10) - 0x8)
 181#define CONFIG_SYS_INIT_RAM_ADDR                CONFIG_SRAM_BASE
 182#define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SRAM_SIZE
 183
 184#define CONFIG_SYS_INIT_SP_OFFSET               \
 185        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 186
 187#define CONFIG_SYS_INIT_SP_ADDR                 \
 188        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 189
 190/*
 191 * SPL related defines
 192 */
 193#define CONFIG_SPL_MAX_SIZE             (CONFIG_SRAM_SIZE - 0xb00)
 194#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
 195
 196/*
 197 * Please select/define only one of the following
 198 * Each definition corresponds to a supported DDR chip.
 199 * DDR configuration is based on the following selection
 200 */
 201#define CONFIG_DDR_MT47H64M16           1
 202#define CONFIG_DDR_MT47H32M16           0
 203#define CONFIG_DDR_MT47H128M8           0
 204
 205/*
 206 * Synchronous/Asynchronous operation of DDR
 207 *
 208 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
 209 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
 210 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
 211 */
 212#define CONFIG_DDR_2HCLK                1
 213#define CONFIG_DDR_HCLK                 0
 214#define CONFIG_DDR_PLL2                 0
 215
 216/*
 217 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
 218 * or not. Modify/Add to only these macros to define new boot types
 219 */
 220#define USB_BOOT_SUPPORTED              0
 221#define PCIE_BOOT_SUPPORTED             0
 222#define SNOR_BOOT_SUPPORTED             1
 223#define NAND_BOOT_SUPPORTED             1
 224#define PNOR_BOOT_SUPPORTED             0
 225#define TFTP_BOOT_SUPPORTED             0
 226#define UART_BOOT_SUPPORTED             0
 227#define SPI_BOOT_SUPPORTED              0
 228#define I2C_BOOT_SUPPORTED              0
 229#define MMC_BOOT_SUPPORTED              0
 230
 231#endif  /* __CONFIG_H */
 232