1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2007-2013 Tensilica, Inc. 4 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 5 */ 6 7#ifndef __CONFIG_H 8#define __CONFIG_H 9 10#include <asm/arch/core.h> 11#include <asm/addrspace.h> 12#include <asm/config.h> 13 14/* 15 * The 'xtfpga' board describes a set of very similar boards with only minimal 16 * differences. 17 */ 18 19/*=====================*/ 20/* Board and Processor */ 21/*=====================*/ 22 23#define CONFIG_XTFPGA 24 25/* FPGA CPU freq after init */ 26#define CONFIG_SYS_CLK_FREQ (gd->cpu_clk) 27 28/*===================*/ 29/* RAM Layout */ 30/*===================*/ 31 32#if XCHAL_HAVE_PTP_MMU 33#define CONFIG_SYS_MEMORY_BASE \ 34 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) 35#define CONFIG_SYS_IO_BASE 0xf0000000 36#else 37#define CONFIG_SYS_MEMORY_BASE 0x60000000 38#define CONFIG_SYS_IO_BASE 0x90000000 39#define CONFIG_MAX_MEM_MAPPED 0x10000000 40#endif 41 42/* Onboard RAM sizes: 43 * 44 * LX60 0x04000000 64 MB 45 * LX110 0x03000000 48 MB 46 * LX200 0x06000000 96 MB 47 * ML605 0x18000000 384 MB 48 * KC705 0x38000000 896 MB 49 * 50 * noMMU configurations can only see first 256MB of onboard memory. 51 */ 52 53#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 54#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE 55#else 56#define CONFIG_SYS_SDRAM_SIZE 0x10000000 57#endif 58 59#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) 60 61/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ 62#ifdef CONFIG_XTFPGA_LX60 63# define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */ 64#else 65# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ 66#endif 67 68#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ 69 70/* Linux boot param area in RAM (used only when booting linux) */ 71#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) 72 73/* Memory test is destructive so default must not overlap vectors or U-Boot*/ 74#define CONFIG_SYS_MEMTEST_START MEMADDR(0x01000000) 75#define CONFIG_SYS_MEMTEST_END MEMADDR(0x02000000) 76 77/* Load address for stand-alone applications. 78 * MEMADDR cannot be used here, because the definition needs to be 79 * a plain number as it's used as -Ttext argument for ld in standalone 80 * example makefile. 81 * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. 82 */ 83#if XCHAL_HAVE_PTP_MMU 84#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR 85#define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 86#else 87#define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 88#endif 89#else 90#define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 91#endif 92 93#if defined(CONFIG_MAX_MEM_MAPPED) && \ 94 CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE 95#define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED 96#else 97#define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE 98#endif 99 100#define XTENSA_SYS_TEXT_ADDR \ 101 (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN) 102 103/* Used by tftpboot; env var 'loadaddr' */ 104#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) 105 106/*==============================*/ 107/* U-Boot general configuration */ 108/*==============================*/ 109 110#define CONFIG_BOARD_POSTCLK_INIT 111 112#define CONFIG_BOOTFILE "uImage" 113 /* Console I/O Buffer Size */ 114#define CONFIG_SYS_CBSIZE 1024 115 /* Boot Argument Buffer Size */ 116#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 117 118/*==============================*/ 119/* U-Boot autoboot configuration */ 120/*==============================*/ 121 122 123/*=========================================*/ 124/* FPGA Registers (board info and control) */ 125/*=========================================*/ 126 127/* 128 * These assume FPGA bitstreams from Tensilica release RB and up. Earlier 129 * releases may not provide any/all of these registers or at these offsets. 130 * Some of the FPGA registers are broken down into bitfields described by 131 * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. 132 */ 133 134/* Date of FPGA bitstream build in binary coded decimal (BCD) */ 135#define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000) 136#define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */ 137#define FPGAREG_MTH_WIDTH 8 138#define FPGAREG_MTH_MASK 0xFF000000 139#define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */ 140#define FPGAREG_DAY_WIDTH 8 141#define FPGAREG_DAY_MASK 0x00FF0000 142#define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/ 143#define FPGAREG_YEAR_WIDTH 16 144#define FPGAREG_YEAR_MASK 0x0000FFFF 145 146/* FPGA core clock frequency in Hz (also input to UART) */ 147#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ 148 149/* 150 * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): 151 * Bits 0..5 set the lower 6 bits of the default ethernet MAC. 152 * Bit 6 is reserved for future use by Tensilica. 153 * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to 154 * the base of flash * (when on/1) or to the base of RAM (when off/0). 155 */ 156#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) 157#define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ 158#define FPGAREG_MAC_WIDTH 6 159#define FPGAREG_MAC_MASK 0x3f 160#define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ 161#define FPGAREG_BOOT_WIDTH 1 162#define FPGAREG_BOOT_MASK 0x80 163#define FPGAREG_BOOT_RAM 0 164#define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT) 165 166/* Force hard reset of board by writing a code to this register */ 167#define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ 168#define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ 169 170/*====================*/ 171/* Serial Driver Info */ 172/*====================*/ 173 174#define CONFIG_SYS_NS16550_SERIAL 175#define CONFIG_SYS_NS16550_REG_SIZE (-4) 176#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ 177 178/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ 179#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ 180#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 181 182/*======================*/ 183/* Ethernet Driver Info */ 184/*======================*/ 185 186#define CONFIG_ETHBASE 00:50:C2:13:6f:00 187#define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000) 188#define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) 189 190/*=====================*/ 191/* Flash & Environment */ 192/*=====================*/ 193 194#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 195#define CONFIG_SYS_MAX_FLASH_BANKS 1 196#ifdef CONFIG_XTFPGA_LX60 197# define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ 198# define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */ 199# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ 200# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) 201# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 202#elif defined(CONFIG_XTFPGA_KC705) 203# define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ 204# define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ 205# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 206# define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000) 207# define CONFIG_SYS_MONITOR_BASE IOADDR(0x06000000) 208#else 209# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ 210# define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ 211# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 212# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) 213# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 214#endif 215#define CONFIG_SYS_MAX_FLASH_SECT \ 216 (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \ 217 CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1) 218 219/* 220 * Put environment in top block (64kB) 221 * Another option would be to put env. in 2nd param block offs 8KB, size 8KB 222 */ 223 224/* print 'E' for empty sector on flinfo */ 225#define CONFIG_SYS_FLASH_EMPTY_INFO 226 227#endif /* __CONFIG_H */ 228