LXR uboot/include/configs/zmx25.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (c) 2011 Graf-Syteco, Matthias Weisser
   4 * <weisserm@arcor.de>
   5 *
   6 * Configuation settings for the zmx25 board
   7 */
   8
   9#ifndef __CONFIG_H
  10#define __CONFIG_H
  11
  12#include <asm/arch/imx-regs.h>
  13
  14#define CONFIG_SYS_TIMER_RATE           32768
  15#define CONFIG_SYS_TIMER_COUNTER        \
  16        (&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
  17
  18#define CONFIG_MACH_TYPE        MACH_TYPE_ZMX25
  19/*
  20 * Environment settings
  21 */
  22#define CONFIG_EXTRA_ENV_SETTINGS \
  23        "gs_fast_boot=setenv bootdelay 5\0" \
  24        "gs_slow_boot=setenv bootdelay 10\0" \
  25        "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
  26                "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
  27                "bootm 0x81000000; bootelf 0x81000000\0"
  28
  29#define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs      */
  30#define CONFIG_SETUP_MEMORY_TAGS
  31#define CONFIG_INITRD_TAG
  32
  33/*
  34 * Hardware drivers
  35 */
  36
  37/*
  38 * Serial
  39 */
  40#define CONFIG_MXC_UART
  41#define CONFIG_MXC_UART_BASE    UART2_BASE
  42
  43/*
  44 * Ethernet
  45 */
  46#define CONFIG_FEC_MXC
  47#define CONFIG_FEC_MXC_PHYADDR          0x00
  48
  49/*
  50 * BOOTP options
  51 */
  52#define CONFIG_BOOTP_BOOTFILESIZE
  53
  54/*
  55 * Command line configuration.
  56 */
  57
  58/*
  59 * Additional command
  60 */
  61
  62/*
  63 * USB
  64 */
  65#ifdef CONFIG_CMD_USB
  66#define CONFIG_USB_EHCI_MXC
  67#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  68#define CONFIG_MXC_USB_PORT     1
  69#define CONFIG_MXC_USB_PORTSC   MXC_EHCI_MODE_SERIAL
  70#define CONFIG_MXC_USB_FLAGS    (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
  71#define CONFIG_EHCI_IS_TDI
  72#endif /* CONFIG_CMD_USB */
  73
  74/* SDRAM */
  75#define PHYS_SDRAM              0x80000000      /* start address of LPDDRRAM */
  76#define PHYS_SDRAM_SIZE         0x04000000      /* 64 megs */
  77
  78#define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
  79#define CONFIG_SYS_INIT_SP_ADDR 0x78020000      /* end of internal SRAM */
  80
  81/*
  82 * FLASH and environment organization
  83 */
  84#define CONFIG_SYS_FLASH_BASE           0xA0000000
  85#define CONFIG_SYS_MAX_FLASH_BANKS      1
  86#define CONFIG_SYS_MAX_FLASH_SECT       256
  87
  88/*
  89 * CFI FLASH driver setup
  90 */
  91
  92#define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_SDRAM_BASE
  93
  94#define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM + (512*1024))
  95#define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM + PHYS_SDRAM_SIZE)
  96
  97
  98/*
  99 * Size of malloc() pool
 100 */
 101#define CONFIG_SYS_MALLOC_LEN           (0x400000 - 0x8000)
 102
 103#endif  /* __CONFIG_H */
 104