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13#ifndef __LINUX_MTD_RAWNAND_H
14#define __LINUX_MTD_RAWNAND_H
15
16#include <config.h>
17
18#include <dm/device.h>
19#include <linux/compat.h>
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/flashchip.h>
22#include <linux/mtd/bbm.h>
23#include <asm/cache.h>
24
25struct mtd_info;
26struct nand_chip;
27struct nand_flash_dev;
28struct device_node;
29
30
31struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
32 struct nand_chip *chip,
33 int *maf_id, int *dev_id,
34 struct nand_flash_dev *type);
35
36
37int nand_scan(struct mtd_info *mtd, int max_chips);
38
39
40
41
42int nand_scan_ident(struct mtd_info *mtd, int max_chips,
43 struct nand_flash_dev *table);
44int nand_scan_tail(struct mtd_info *mtd);
45
46
47void nand_release(struct mtd_info *mtd);
48
49
50void nand_wait_ready(struct mtd_info *mtd);
51
52
53
54
55
56
57#define NAND_MAX_OOBSIZE 1664
58#define NAND_MAX_PAGESIZE 16384
59
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61
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64
65
66
67#define NAND_NCE 0x01
68
69#define NAND_CLE 0x02
70
71#define NAND_ALE 0x04
72
73#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
74#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
75#define NAND_CTRL_CHANGE 0x80
76
77
78
79
80#define NAND_CMD_READ0 0
81#define NAND_CMD_READ1 1
82#define NAND_CMD_RNDOUT 5
83#define NAND_CMD_PAGEPROG 0x10
84#define NAND_CMD_READOOB 0x50
85#define NAND_CMD_ERASE1 0x60
86#define NAND_CMD_STATUS 0x70
87#define NAND_CMD_SEQIN 0x80
88#define NAND_CMD_RNDIN 0x85
89#define NAND_CMD_READID 0x90
90#define NAND_CMD_ERASE2 0xd0
91#define NAND_CMD_PARAM 0xec
92#define NAND_CMD_GET_FEATURES 0xee
93#define NAND_CMD_SET_FEATURES 0xef
94#define NAND_CMD_RESET 0xff
95
96#define NAND_CMD_LOCK 0x2a
97#define NAND_CMD_UNLOCK1 0x23
98#define NAND_CMD_UNLOCK2 0x24
99
100
101#define NAND_CMD_READSTART 0x30
102#define NAND_CMD_RNDOUTSTART 0xE0
103#define NAND_CMD_CACHEDPROG 0x15
104
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110
111
112#define NAND_CMD_DEPLETE1 0x100
113#define NAND_CMD_DEPLETE2 0x38
114#define NAND_CMD_STATUS_MULTI 0x71
115#define NAND_CMD_STATUS_ERROR 0x72
116
117#define NAND_CMD_STATUS_ERROR0 0x73
118#define NAND_CMD_STATUS_ERROR1 0x74
119#define NAND_CMD_STATUS_ERROR2 0x75
120#define NAND_CMD_STATUS_ERROR3 0x76
121#define NAND_CMD_STATUS_RESET 0x7f
122#define NAND_CMD_STATUS_CLEAR 0xff
123
124#define NAND_CMD_NONE -1
125
126
127#define NAND_STATUS_FAIL 0x01
128#define NAND_STATUS_FAIL_N1 0x02
129#define NAND_STATUS_TRUE_READY 0x20
130#define NAND_STATUS_READY 0x40
131#define NAND_STATUS_WP 0x80
132
133#define NAND_DATA_IFACE_CHECK_ONLY -1
134
135
136
137
138typedef enum {
139 NAND_ECC_NONE,
140 NAND_ECC_SOFT,
141 NAND_ECC_HW,
142 NAND_ECC_HW_SYNDROME,
143 NAND_ECC_HW_OOB_FIRST,
144 NAND_ECC_SOFT_BCH,
145} nand_ecc_modes_t;
146
147enum nand_ecc_algo {
148 NAND_ECC_UNKNOWN,
149 NAND_ECC_HAMMING,
150 NAND_ECC_BCH,
151};
152
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155
156
157#define NAND_ECC_READ 0
158
159#define NAND_ECC_WRITE 1
160
161#define NAND_ECC_READSYN 2
162
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168
169#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
170#define NAND_ECC_MAXIMIZE BIT(1)
171
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175
176#define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
177
178
179#define NAND_GET_DEVICE 0x80
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185
186
187#define NAND_BUSWIDTH_16 0x00000002
188
189#define NAND_NO_PADDING 0x00000004
190
191#define NAND_CACHEPRG 0x00000008
192
193#define NAND_COPYBACK 0x00000010
194
195
196
197
198
199#define NAND_NEED_READRDY 0x00000100
200
201
202#define NAND_NO_SUBPAGE_WRITE 0x00000200
203
204
205#define NAND_BROKEN_XD 0x00000400
206
207
208#define NAND_ROM 0x00000800
209
210
211#define NAND_SUBPAGE_READ 0x00001000
212
213
214
215
216
217#define NAND_NEED_SCRAMBLING 0x00002000
218
219
220#define NAND_ROW_ADDR_3 0x00004000
221
222
223#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
224
225
226#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
227#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
228#define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
229
230
231
232#define NAND_SKIP_BBTSCAN 0x00010000
233
234
235
236
237#define NAND_OWN_BUFFERS 0x00020000
238
239#define NAND_SCAN_SILENT_NODEV 0x00040000
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244
245
246#define NAND_BUSWIDTH_AUTO 0x00080000
247
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249
250
251#define NAND_USE_BOUNCE_BUFFER 0x00100000
252
253
254
255#define NAND_BBT_SCANNED 0x40000000
256
257#define NAND_CONTROLLER_ALLOC 0x80000000
258
259
260#define NAND_CI_CHIPNR_MSK 0x03
261#define NAND_CI_CELLTYPE_MSK 0x0C
262#define NAND_CI_CELLTYPE_SHIFT 2
263
264
265#define ONFI_FEATURE_16_BIT_BUS (1 << 0)
266#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
267
268
269#define ONFI_TIMING_MODE_0 (1 << 0)
270#define ONFI_TIMING_MODE_1 (1 << 1)
271#define ONFI_TIMING_MODE_2 (1 << 2)
272#define ONFI_TIMING_MODE_3 (1 << 3)
273#define ONFI_TIMING_MODE_4 (1 << 4)
274#define ONFI_TIMING_MODE_5 (1 << 5)
275#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
276
277
278#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
279
280
281#define ONFI_FEATURE_ADDR_READ_RETRY 0x89
282
283
284#define ONFI_SUBFEATURE_PARAM_LEN 4
285
286
287#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
288
289struct nand_onfi_params {
290
291
292 u8 sig[4];
293 __le16 revision;
294 __le16 features;
295 __le16 opt_cmd;
296 u8 reserved0[2];
297 __le16 ext_param_page_length;
298 u8 num_of_param_pages;
299 u8 reserved1[17];
300
301
302 char manufacturer[12];
303 char model[20];
304 u8 jedec_id;
305 __le16 date_code;
306 u8 reserved2[13];
307
308
309 __le32 byte_per_page;
310 __le16 spare_bytes_per_page;
311 __le32 data_bytes_per_ppage;
312 __le16 spare_bytes_per_ppage;
313 __le32 pages_per_block;
314 __le32 blocks_per_lun;
315 u8 lun_count;
316 u8 addr_cycles;
317 u8 bits_per_cell;
318 __le16 bb_per_lun;
319 __le16 block_endurance;
320 u8 guaranteed_good_blocks;
321 __le16 guaranteed_block_endurance;
322 u8 programs_per_page;
323 u8 ppage_attr;
324 u8 ecc_bits;
325 u8 interleaved_bits;
326 u8 interleaved_ops;
327 u8 reserved3[13];
328
329
330 u8 io_pin_capacitance_max;
331 __le16 async_timing_mode;
332 __le16 program_cache_timing_mode;
333 __le16 t_prog;
334 __le16 t_bers;
335 __le16 t_r;
336 __le16 t_ccs;
337 __le16 src_sync_timing_mode;
338 u8 src_ssync_features;
339 __le16 clk_pin_capacitance_typ;
340 __le16 io_pin_capacitance_typ;
341 __le16 input_pin_capacitance_typ;
342 u8 input_pin_capacitance_max;
343 u8 driver_strength_support;
344 __le16 t_int_r;
345 __le16 t_adl;
346 u8 reserved4[8];
347
348
349 __le16 vendor_revision;
350 u8 vendor[88];
351
352 __le16 crc;
353} __packed;
354
355#define ONFI_CRC_BASE 0x4F4E
356
357
358struct onfi_ext_ecc_info {
359 u8 ecc_bits;
360 u8 codeword_size;
361 __le16 bb_per_lun;
362 __le16 block_endurance;
363 u8 reserved[2];
364} __packed;
365
366#define ONFI_SECTION_TYPE_0 0
367#define ONFI_SECTION_TYPE_1 1
368#define ONFI_SECTION_TYPE_2 2
369struct onfi_ext_section {
370 u8 type;
371 u8 length;
372} __packed;
373
374#define ONFI_EXT_SECTION_MAX 8
375
376
377struct onfi_ext_param_page {
378 __le16 crc;
379 u8 sig[4];
380 u8 reserved0[10];
381 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
382
383
384
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387
388
389} __packed;
390
391struct nand_onfi_vendor_micron {
392 u8 two_plane_read;
393 u8 read_cache;
394 u8 read_unique_id;
395 u8 dq_imped;
396 u8 dq_imped_num_settings;
397 u8 dq_imped_feat_addr;
398 u8 rb_pulldown_strength;
399 u8 rb_pulldown_strength_feat_addr;
400 u8 rb_pulldown_strength_num_settings;
401 u8 otp_mode;
402 u8 otp_page_start;
403 u8 otp_data_prot_addr;
404 u8 otp_num_pages;
405 u8 otp_feat_addr;
406 u8 read_retry_options;
407 u8 reserved[72];
408 u8 param_revision;
409} __packed;
410
411struct jedec_ecc_info {
412 u8 ecc_bits;
413 u8 codeword_size;
414 __le16 bb_per_lun;
415 __le16 block_endurance;
416 u8 reserved[2];
417} __packed;
418
419
420#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
421
422struct nand_jedec_params {
423
424
425 u8 sig[4];
426 __le16 revision;
427 __le16 features;
428 u8 opt_cmd[3];
429 __le16 sec_cmd;
430 u8 num_of_param_pages;
431 u8 reserved0[18];
432
433
434 char manufacturer[12];
435 char model[20];
436 u8 jedec_id[6];
437 u8 reserved1[10];
438
439
440 __le32 byte_per_page;
441 __le16 spare_bytes_per_page;
442 u8 reserved2[6];
443 __le32 pages_per_block;
444 __le32 blocks_per_lun;
445 u8 lun_count;
446 u8 addr_cycles;
447 u8 bits_per_cell;
448 u8 programs_per_page;
449 u8 multi_plane_addr;
450 u8 multi_plane_op_attr;
451 u8 reserved3[38];
452
453
454 __le16 async_sdr_speed_grade;
455 __le16 toggle_ddr_speed_grade;
456 __le16 sync_ddr_speed_grade;
457 u8 async_sdr_features;
458 u8 toggle_ddr_features;
459 u8 sync_ddr_features;
460 __le16 t_prog;
461 __le16 t_bers;
462 __le16 t_r;
463 __le16 t_r_multi_plane;
464 __le16 t_ccs;
465 __le16 io_pin_capacitance_typ;
466 __le16 input_pin_capacitance_typ;
467 __le16 clk_pin_capacitance_typ;
468 u8 driver_strength_support;
469 __le16 t_adl;
470 u8 reserved4[36];
471
472
473 u8 guaranteed_good_blocks;
474 __le16 guaranteed_block_endurance;
475 struct jedec_ecc_info ecc_info[4];
476 u8 reserved5[29];
477
478
479 u8 reserved6[148];
480
481
482 __le16 vendor_rev_num;
483 u8 reserved7[88];
484
485
486 __le16 crc;
487} __packed;
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496
497struct nand_hw_control {
498 spinlock_t lock;
499 struct nand_chip *active;
500};
501
502static inline void nand_hw_control_init(struct nand_hw_control *nfc)
503{
504 nfc->active = NULL;
505 spin_lock_init(&nfc->lock);
506 init_waitqueue_head(&nfc->wq);
507}
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514
515struct nand_ecc_step_info {
516 int stepsize;
517 const int *strengths;
518 int nstrengths;
519};
520
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526
527struct nand_ecc_caps {
528 const struct nand_ecc_step_info *stepinfos;
529 int nstepinfos;
530 int (*calc_ecc_bytes)(int step_size, int strength);
531};
532
533
534#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
535static const int __name##_strengths[] = { __VA_ARGS__ }; \
536static const struct nand_ecc_step_info __name##_stepinfo = { \
537 .stepsize = __step, \
538 .strengths = __name##_strengths, \
539 .nstrengths = ARRAY_SIZE(__name##_strengths), \
540}; \
541static const struct nand_ecc_caps __name = { \
542 .stepinfos = &__name##_stepinfo, \
543 .nstepinfos = 1, \
544 .calc_ecc_bytes = __calc, \
545}
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599struct nand_ecc_ctrl {
600 nand_ecc_modes_t mode;
601 enum nand_ecc_algo algo;
602 int steps;
603 int size;
604 int bytes;
605 int total;
606 int strength;
607 int prepad;
608 int postpad;
609 unsigned int options;
610 struct nand_ecclayout *layout;
611 void *priv;
612 void (*hwctl)(struct mtd_info *mtd, int mode);
613 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
614 uint8_t *ecc_code);
615 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
616 uint8_t *calc_ecc);
617 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
618 uint8_t *buf, int oob_required, int page);
619 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
620 const uint8_t *buf, int oob_required, int page);
621 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
622 uint8_t *buf, int oob_required, int page);
623 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
624 uint32_t offs, uint32_t len, uint8_t *buf, int page);
625 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
626 uint32_t offset, uint32_t data_len,
627 const uint8_t *data_buf, int oob_required, int page);
628 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
629 const uint8_t *buf, int oob_required, int page);
630 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
631 int page);
632 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
633 int page);
634 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
635 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
636 int page);
637};
638
639static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
640{
641 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
642}
643
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651
652
653struct nand_buffers {
654 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
655 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
656 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
657 ARCH_DMA_MINALIGN)];
658};
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711struct nand_sdr_timings {
712 u64 tBERS_max;
713 u32 tCCS_min;
714 u64 tPROG_max;
715 u64 tR_max;
716 u32 tALH_min;
717 u32 tADL_min;
718 u32 tALS_min;
719 u32 tAR_min;
720 u32 tCEA_max;
721 u32 tCEH_min;
722 u32 tCH_min;
723 u32 tCHZ_max;
724 u32 tCLH_min;
725 u32 tCLR_min;
726 u32 tCLS_min;
727 u32 tCOH_min;
728 u32 tCS_min;
729 u32 tDH_min;
730 u32 tDS_min;
731 u32 tFEAT_max;
732 u32 tIR_min;
733 u32 tITC_max;
734 u32 tRC_min;
735 u32 tREA_max;
736 u32 tREH_min;
737 u32 tRHOH_min;
738 u32 tRHW_min;
739 u32 tRHZ_max;
740 u32 tRLOH_min;
741 u32 tRP_min;
742 u32 tRR_min;
743 u64 tRST_max;
744 u32 tWB_max;
745 u32 tWC_min;
746 u32 tWH_min;
747 u32 tWHR_min;
748 u32 tWP_min;
749 u32 tWW_min;
750};
751
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755
756enum nand_data_interface_type {
757 NAND_SDR_IFACE,
758};
759
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764
765struct nand_data_interface {
766 enum nand_data_interface_type type;
767 union {
768 struct nand_sdr_timings sdr;
769 } timings;
770};
771
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774
775
776static inline const struct nand_sdr_timings *
777nand_get_sdr_timings(const struct nand_data_interface *conf)
778{
779 if (conf->type != NAND_SDR_IFACE)
780 return ERR_PTR(-EINVAL);
781
782 return &conf->timings.sdr;
783}
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888struct nand_chip {
889 struct mtd_info mtd;
890 void __iomem *IO_ADDR_R;
891 void __iomem *IO_ADDR_W;
892
893 int flash_node;
894
895 uint8_t (*read_byte)(struct mtd_info *mtd);
896 u16 (*read_word)(struct mtd_info *mtd);
897 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
898 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
899 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
900 void (*select_chip)(struct mtd_info *mtd, int chip);
901 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
902 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
903 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
904 int (*dev_ready)(struct mtd_info *mtd);
905 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
906 int page_addr);
907 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
908 int (*erase)(struct mtd_info *mtd, int page);
909 int (*scan_bbt)(struct mtd_info *mtd);
910 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
911 uint32_t offset, int data_len, const uint8_t *buf,
912 int oob_required, int page, int raw);
913 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
914 int feature_addr, uint8_t *subfeature_para);
915 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
916 int feature_addr, uint8_t *subfeature_para);
917 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
918 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
919 const struct nand_data_interface *conf);
920
921
922 int chip_delay;
923 unsigned int options;
924 unsigned int bbt_options;
925
926 int page_shift;
927 int phys_erase_shift;
928 int bbt_erase_shift;
929 int chip_shift;
930 int numchips;
931 uint64_t chipsize;
932 int pagemask;
933 int pagebuf;
934 unsigned int pagebuf_bitflips;
935 int subpagesize;
936 uint8_t bits_per_cell;
937 uint16_t ecc_strength_ds;
938 uint16_t ecc_step_ds;
939 int onfi_timing_mode_default;
940 int badblockpos;
941 int badblockbits;
942
943 int onfi_version;
944 int jedec_version;
945 struct nand_onfi_params onfi_params;
946 struct nand_jedec_params jedec_params;
947
948 struct nand_data_interface *data_interface;
949
950 int read_retries;
951
952 flstate_t state;
953
954 uint8_t *oob_poi;
955 struct nand_hw_control *controller;
956 struct nand_ecclayout *ecclayout;
957
958 struct nand_ecc_ctrl ecc;
959 struct nand_buffers *buffers;
960 unsigned long buf_align;
961 struct nand_hw_control hwcontrol;
962
963 uint8_t *bbt;
964 struct nand_bbt_descr *bbt_td;
965 struct nand_bbt_descr *bbt_md;
966
967 struct nand_bbt_descr *badblock_pattern;
968
969 void *priv;
970};
971
972static inline void nand_set_flash_node(struct nand_chip *chip,
973 ofnode node)
974{
975 chip->flash_node = ofnode_to_offset(node);
976}
977
978static inline ofnode nand_get_flash_node(struct nand_chip *chip)
979{
980 return offset_to_ofnode(chip->flash_node);
981}
982
983static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
984{
985 return container_of(mtd, struct nand_chip, mtd);
986}
987
988static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
989{
990 return &chip->mtd;
991}
992
993static inline void *nand_get_controller_data(struct nand_chip *chip)
994{
995 return chip->priv;
996}
997
998static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
999{
1000 chip->priv = priv;
1001}
1002
1003
1004
1005
1006#define NAND_MFR_TOSHIBA 0x98
1007#define NAND_MFR_SAMSUNG 0xec
1008#define NAND_MFR_FUJITSU 0x04
1009#define NAND_MFR_NATIONAL 0x8f
1010#define NAND_MFR_RENESAS 0x07
1011#define NAND_MFR_STMICRO 0x20
1012#define NAND_MFR_HYNIX 0xad
1013#define NAND_MFR_MICRON 0x2c
1014#define NAND_MFR_AMD 0x01
1015#define NAND_MFR_MACRONIX 0xc2
1016#define NAND_MFR_EON 0x92
1017#define NAND_MFR_SANDISK 0x45
1018#define NAND_MFR_INTEL 0x89
1019#define NAND_MFR_ATO 0x9b
1020
1021
1022#define NAND_MAX_ID_LEN 8
1023
1024
1025
1026
1027
1028
1029#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1030 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1031 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1044 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1045 .options = (opts) }
1046
1047#define NAND_ECC_INFO(_strength, _step) \
1048 { .strength_ds = (_strength), .step_ds = (_step) }
1049#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1050#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
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1067
1068
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1070
1071
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1073
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1079
1080
1081struct nand_flash_dev {
1082 char *name;
1083 union {
1084 struct {
1085 uint8_t mfr_id;
1086 uint8_t dev_id;
1087 };
1088 uint8_t id[NAND_MAX_ID_LEN];
1089 };
1090 unsigned int pagesize;
1091 unsigned int chipsize;
1092 unsigned int erasesize;
1093 unsigned int options;
1094 uint16_t id_len;
1095 uint16_t oobsize;
1096 struct {
1097 uint16_t strength_ds;
1098 uint16_t step_ds;
1099 } ecc;
1100 int onfi_timing_mode_default;
1101};
1102
1103
1104
1105
1106
1107
1108struct nand_manufacturers {
1109 int id;
1110 char *name;
1111};
1112
1113extern struct nand_flash_dev nand_flash_ids[];
1114extern struct nand_manufacturers nand_manuf_ids[];
1115
1116int nand_default_bbt(struct mtd_info *mtd);
1117int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1118int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1119int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1120int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1121 int allowbbt);
1122int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1123 size_t *retlen, uint8_t *buf);
1124
1125
1126
1127
1128#define NAND_SMALL_BADBLOCK_POS 5
1129#define NAND_LARGE_BADBLOCK_POS 0
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142struct platform_nand_chip {
1143 int nr_chips;
1144 int chip_offset;
1145 int nr_partitions;
1146 struct mtd_partition *partitions;
1147 int chip_delay;
1148 unsigned int options;
1149 unsigned int bbt_options;
1150 const char **part_probe_types;
1151};
1152
1153
1154struct platform_device;
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172struct platform_nand_ctrl {
1173 int (*probe)(struct platform_device *pdev);
1174 void (*remove)(struct platform_device *pdev);
1175 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1176 int (*dev_ready)(struct mtd_info *mtd);
1177 void (*select_chip)(struct mtd_info *mtd, int chip);
1178 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1179 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1180 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1181 unsigned char (*read_byte)(struct mtd_info *mtd);
1182 void *priv;
1183};
1184
1185
1186
1187
1188
1189
1190struct platform_nand_data {
1191 struct platform_nand_chip chip;
1192 struct platform_nand_ctrl ctrl;
1193};
1194
1195#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1196
1197static inline int onfi_feature(struct nand_chip *chip)
1198{
1199 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1200}
1201
1202
1203static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1204{
1205 if (!chip->onfi_version)
1206 return ONFI_TIMING_MODE_UNKNOWN;
1207 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1208}
1209
1210
1211static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1212{
1213 if (!chip->onfi_version)
1214 return ONFI_TIMING_MODE_UNKNOWN;
1215 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1216}
1217#else
1218static inline int onfi_feature(struct nand_chip *chip)
1219{
1220 return 0;
1221}
1222
1223static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1224{
1225 return ONFI_TIMING_MODE_UNKNOWN;
1226}
1227
1228static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1229{
1230 return ONFI_TIMING_MODE_UNKNOWN;
1231}
1232#endif
1233
1234int onfi_init_data_interface(struct nand_chip *chip,
1235 struct nand_data_interface *iface,
1236 enum nand_data_interface_type type,
1237 int timing_mode);
1238
1239
1240
1241
1242
1243
1244static inline bool nand_is_slc(struct nand_chip *chip)
1245{
1246 return chip->bits_per_cell == 1;
1247}
1248
1249
1250
1251
1252
1253static inline int nand_opcode_8bits(unsigned int command)
1254{
1255 switch (command) {
1256 case NAND_CMD_READID:
1257 case NAND_CMD_PARAM:
1258 case NAND_CMD_GET_FEATURES:
1259 case NAND_CMD_SET_FEATURES:
1260 return 1;
1261 default:
1262 break;
1263 }
1264 return 0;
1265}
1266
1267
1268static inline int jedec_feature(struct nand_chip *chip)
1269{
1270 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1271 : 0;
1272}
1273
1274
1275void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1276void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1277void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1278void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1279uint8_t nand_read_byte(struct mtd_info *mtd);
1280
1281
1282const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1283
1284const struct nand_data_interface *nand_get_default_data_interface(void);
1285
1286int nand_check_erased_ecc_chunk(void *data, int datalen,
1287 void *ecc, int ecclen,
1288 void *extraoob, int extraooblen,
1289 int threshold);
1290
1291int nand_check_ecc_caps(struct nand_chip *chip,
1292 const struct nand_ecc_caps *caps, int oobavail);
1293
1294int nand_match_ecc_req(struct nand_chip *chip,
1295 const struct nand_ecc_caps *caps, int oobavail);
1296
1297int nand_maximize_ecc(struct nand_chip *chip,
1298 const struct nand_ecc_caps *caps, int oobavail);
1299
1300
1301int nand_reset(struct nand_chip *chip, int chipnr);
1302
1303
1304int nand_reset_op(struct nand_chip *chip);
1305int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1306 unsigned int len);
1307int nand_status_op(struct nand_chip *chip, u8 *status);
1308int nand_exit_status_op(struct nand_chip *chip);
1309int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1310int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1311 unsigned int offset_in_page, void *buf, unsigned int len);
1312int nand_change_read_column_op(struct nand_chip *chip,
1313 unsigned int offset_in_page, void *buf,
1314 unsigned int len, bool force_8bit);
1315int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1316 unsigned int offset_in_page, void *buf, unsigned int len);
1317int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1318 unsigned int offset_in_page, const void *buf,
1319 unsigned int len);
1320int nand_prog_page_end_op(struct nand_chip *chip);
1321int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1322 unsigned int offset_in_page, const void *buf,
1323 unsigned int len);
1324int nand_change_write_column_op(struct nand_chip *chip,
1325 unsigned int offset_in_page, const void *buf,
1326 unsigned int len, bool force_8bit);
1327int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1328 bool force_8bit);
1329int nand_write_data_op(struct nand_chip *chip, const void *buf,
1330 unsigned int len, bool force_8bit);
1331
1332#endif
1333