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6
7#include <common.h>
8#include <cpu_func.h>
9#include <env.h>
10#include <fsl_ddr_sdram.h>
11#include <init.h>
12#include <hang.h>
13#include <vsprintf.h>
14#include <asm/io.h>
15#include <linux/errno.h>
16#include <asm/system.h>
17#include <fm_eth.h>
18#include <asm/armv8/mmu.h>
19#include <asm/io.h>
20#include <asm/arch/fsl_serdes.h>
21#include <asm/arch/soc.h>
22#include <asm/arch/cpu.h>
23#include <asm/arch/speed.h>
24#include <fsl_immap.h>
25#include <asm/arch/mp.h>
26#include <efi_loader.h>
27#include <fsl-mc/fsl_mc.h>
28#ifdef CONFIG_FSL_ESDHC
29#include <fsl_esdhc.h>
30#endif
31#include <asm/armv8/sec_firmware.h>
32#ifdef CONFIG_SYS_FSL_DDR
33#include <fsl_ddr.h>
34#endif
35#include <asm/arch/clock.h>
36#include <hwconfig.h>
37#include <fsl_qbman.h>
38
39#ifdef CONFIG_TFABOOT
40#include <env_internal.h>
41#ifdef CONFIG_CHAIN_OF_TRUST
42#include <fsl_validate.h>
43#endif
44#endif
45#include <linux/mii.h>
46
47DECLARE_GLOBAL_DATA_PTR;
48
49static struct cpu_type cpu_type_list[] = {
50 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
51 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
52 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
53 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
54 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
55 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
56 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
57 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
58 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
59 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
60 CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
61 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
62 CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
63 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
64 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
65 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
66 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
67 CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
68 CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
69 CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
70 CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
71 CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
72 CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
73 CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
74 CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
75 CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
76 CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
77 CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
78};
79
80#define EARLY_PGTABLE_SIZE 0x5000
81static struct mm_region early_map[] = {
82#ifdef CONFIG_FSL_LSCH3
83 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
84 CONFIG_SYS_FSL_CCSR_SIZE,
85 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
86 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
87 },
88 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
89 SYS_FSL_OCRAM_SPACE_SIZE,
90 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
91 },
92 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
93 CONFIG_SYS_FSL_QSPI_SIZE1,
94 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
95#ifdef CONFIG_FSL_IFC
96
97 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
98 CONFIG_SYS_FSL_IFC_SIZE1_1,
99 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
100 },
101 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
102 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
103 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
104 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
105 },
106 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
107 CONFIG_SYS_FSL_IFC_SIZE1,
108 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
109 },
110#endif
111 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
112 CONFIG_SYS_FSL_DRAM_SIZE1,
113#if defined(CONFIG_TFABOOT) || \
114 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
115 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
116#else
117 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
118#endif
119 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
120 },
121#ifdef CONFIG_FSL_IFC
122
123 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
124 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
125 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
126 },
127#endif
128 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
129 CONFIG_SYS_FSL_DCSR_SIZE,
130 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
131 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
132 },
133 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
134 CONFIG_SYS_FSL_DRAM_SIZE2,
135 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
136 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
137 },
138#ifdef CONFIG_SYS_FSL_DRAM_BASE3
139 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
140 CONFIG_SYS_FSL_DRAM_SIZE3,
141 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
142 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
143 },
144#endif
145#elif defined(CONFIG_FSL_LSCH2)
146 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
147 CONFIG_SYS_FSL_CCSR_SIZE,
148 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
149 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
150 },
151 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
152 SYS_FSL_OCRAM_SPACE_SIZE,
153 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
154 },
155 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
156 CONFIG_SYS_FSL_DCSR_SIZE,
157 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
158 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
159 },
160 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
161 CONFIG_SYS_FSL_QSPI_SIZE,
162 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
163 },
164#ifdef CONFIG_FSL_IFC
165 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
166 CONFIG_SYS_FSL_IFC_SIZE,
167 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
168 },
169#endif
170 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
171 CONFIG_SYS_FSL_DRAM_SIZE1,
172#if defined(CONFIG_TFABOOT) || \
173 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
174 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
175#else
176 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
177#endif
178 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
179 },
180 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
181 CONFIG_SYS_FSL_DRAM_SIZE2,
182 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
183 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
184 },
185#endif
186 {},
187};
188
189static struct mm_region final_map[] = {
190#ifdef CONFIG_FSL_LSCH3
191 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
192 CONFIG_SYS_FSL_CCSR_SIZE,
193 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
194 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
195 },
196 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
197 SYS_FSL_OCRAM_SPACE_SIZE,
198 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
199 },
200 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
201 CONFIG_SYS_FSL_DRAM_SIZE1,
202 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
203 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
204 },
205 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
206 CONFIG_SYS_FSL_QSPI_SIZE1,
207 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
208 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
209 },
210 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
211 CONFIG_SYS_FSL_QSPI_SIZE2,
212 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
213 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
214 },
215#ifdef CONFIG_FSL_IFC
216 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
217 CONFIG_SYS_FSL_IFC_SIZE2,
218 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
219 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
220 },
221#endif
222 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
223 CONFIG_SYS_FSL_DCSR_SIZE,
224 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
225 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
226 },
227 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
228 CONFIG_SYS_FSL_MC_SIZE,
229 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
230 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
231 },
232 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
233 CONFIG_SYS_FSL_NI_SIZE,
234 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
235 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
236 },
237
238 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
239 CONFIG_SYS_FSL_QBMAN_SIZE_1,
240 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
241 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
242 },
243 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
244 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
245 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
246 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
247 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
248 },
249 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
250 CONFIG_SYS_PCIE1_PHYS_SIZE,
251 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
252 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
253 },
254 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
255 CONFIG_SYS_PCIE2_PHYS_SIZE,
256 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
257 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
258 },
259#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
260 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
261 CONFIG_SYS_PCIE3_PHYS_SIZE,
262 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
263 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
264 },
265#endif
266#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
267 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
268 CONFIG_SYS_PCIE4_PHYS_SIZE,
269 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
270 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
271 },
272#endif
273#ifdef SYS_PCIE5_PHYS_ADDR
274 { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
275 SYS_PCIE5_PHYS_SIZE,
276 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
277 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
278 },
279#endif
280#ifdef SYS_PCIE6_PHYS_ADDR
281 { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
282 SYS_PCIE6_PHYS_SIZE,
283 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
284 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
285 },
286#endif
287 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
288 CONFIG_SYS_FSL_WRIOP1_SIZE,
289 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
290 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
291 },
292 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
293 CONFIG_SYS_FSL_AIOP1_SIZE,
294 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
295 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
296 },
297 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
298 CONFIG_SYS_FSL_PEBUF_SIZE,
299 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
300 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
301 },
302 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
303 CONFIG_SYS_FSL_DRAM_SIZE2,
304 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
305 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
306 },
307#ifdef CONFIG_SYS_FSL_DRAM_BASE3
308 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
309 CONFIG_SYS_FSL_DRAM_SIZE3,
310 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
311 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
312 },
313#endif
314#elif defined(CONFIG_FSL_LSCH2)
315 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
316 CONFIG_SYS_FSL_BOOTROM_SIZE,
317 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
318 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
319 },
320 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
321 CONFIG_SYS_FSL_CCSR_SIZE,
322 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
323 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
324 },
325 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
326 SYS_FSL_OCRAM_SPACE_SIZE,
327 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
328 },
329 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
330 CONFIG_SYS_FSL_DCSR_SIZE,
331 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
332 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
333 },
334 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
335 CONFIG_SYS_FSL_QSPI_SIZE,
336 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
337 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
338 },
339#ifdef CONFIG_FSL_IFC
340 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
341 CONFIG_SYS_FSL_IFC_SIZE,
342 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
343 },
344#endif
345 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
346 CONFIG_SYS_FSL_DRAM_SIZE1,
347 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
348 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
349 },
350 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
351 CONFIG_SYS_FSL_QBMAN_SIZE,
352 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
353 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
354 },
355 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
356 CONFIG_SYS_FSL_DRAM_SIZE2,
357 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
358 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
359 },
360 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
361 CONFIG_SYS_PCIE1_PHYS_SIZE,
362 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
363 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
364 },
365 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
366 CONFIG_SYS_PCIE2_PHYS_SIZE,
367 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
368 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
369 },
370#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
371 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
372 CONFIG_SYS_PCIE3_PHYS_SIZE,
373 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
374 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
375 },
376#endif
377 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
378 CONFIG_SYS_FSL_DRAM_SIZE3,
379 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
380 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
381 },
382#endif
383#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
384 {},
385#endif
386 {},
387};
388
389struct mm_region *mem_map = early_map;
390
391void cpu_name(char *name)
392{
393 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
394 unsigned int i, svr, ver;
395
396 svr = gur_in32(&gur->svr);
397 ver = SVR_SOC_VER(svr);
398
399 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
400 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
401 strcpy(name, cpu_type_list[i].name);
402#ifdef CONFIG_ARCH_LX2160A
403 if (IS_C_PROCESSOR(svr))
404 strcat(name, "C");
405#endif
406
407 if (IS_E_PROCESSOR(svr))
408 strcat(name, "E");
409
410 sprintf(name + strlen(name), " Rev%d.%d",
411 SVR_MAJ(svr), SVR_MIN(svr));
412 break;
413 }
414
415 if (i == ARRAY_SIZE(cpu_type_list))
416 strcpy(name, "unknown");
417}
418
419#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
420
421
422
423
424
425
426
427
428
429static inline void early_mmu_setup(void)
430{
431 unsigned int el = current_el();
432
433
434 if (el == 3)
435 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
436 else
437 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
438 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
439 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
440
441
442 setup_pgtables();
443
444
445 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
446 get_tcr(el, NULL, NULL) &
447 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
448 MEMORY_ATTRIBUTES);
449
450 set_sctlr(get_sctlr() | CR_M);
451}
452
453static void fix_pcie_mmu_map(void)
454{
455#ifdef CONFIG_ARCH_LS2080A
456 unsigned int i;
457 u32 svr, ver;
458 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
459
460 svr = gur_in32(&gur->svr);
461 ver = SVR_SOC_VER(svr);
462
463
464 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
465 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
466 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
467 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
468 switch (final_map[i].phys) {
469 case CONFIG_SYS_PCIE1_PHYS_ADDR:
470 final_map[i].phys = 0x2000000000ULL;
471 final_map[i].virt = 0x2000000000ULL;
472 final_map[i].size = 0x800000000ULL;
473 break;
474 case CONFIG_SYS_PCIE2_PHYS_ADDR:
475 final_map[i].phys = 0x2800000000ULL;
476 final_map[i].virt = 0x2800000000ULL;
477 final_map[i].size = 0x800000000ULL;
478 break;
479#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
480 case CONFIG_SYS_PCIE3_PHYS_ADDR:
481 final_map[i].phys = 0x3000000000ULL;
482 final_map[i].virt = 0x3000000000ULL;
483 final_map[i].size = 0x800000000ULL;
484 break;
485#endif
486#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
487 case CONFIG_SYS_PCIE4_PHYS_ADDR:
488 final_map[i].phys = 0x3800000000ULL;
489 final_map[i].virt = 0x3800000000ULL;
490 final_map[i].size = 0x800000000ULL;
491 break;
492#endif
493 default:
494 break;
495 }
496 }
497 }
498#endif
499}
500
501
502
503
504
505
506
507
508
509static inline void final_mmu_setup(void)
510{
511 u64 tlb_addr_save = gd->arch.tlb_addr;
512 unsigned int el = current_el();
513 int index;
514
515
516 fix_pcie_mmu_map();
517
518 mem_map = final_map;
519
520
521 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
522
523
524
525
526
527 switch (final_map[index].virt) {
528 case CONFIG_SYS_FSL_DRAM_BASE1:
529 final_map[index].virt = gd->bd->bi_dram[0].start;
530 final_map[index].phys = gd->bd->bi_dram[0].start;
531 final_map[index].size = gd->bd->bi_dram[0].size;
532 break;
533#ifdef CONFIG_SYS_FSL_DRAM_BASE2
534 case CONFIG_SYS_FSL_DRAM_BASE2:
535#if (CONFIG_NR_DRAM_BANKS >= 2)
536 final_map[index].virt = gd->bd->bi_dram[1].start;
537 final_map[index].phys = gd->bd->bi_dram[1].start;
538 final_map[index].size = gd->bd->bi_dram[1].size;
539#else
540 final_map[index].size = 0;
541#endif
542 break;
543#endif
544#ifdef CONFIG_SYS_FSL_DRAM_BASE3
545 case CONFIG_SYS_FSL_DRAM_BASE3:
546#if (CONFIG_NR_DRAM_BANKS >= 3)
547 final_map[index].virt = gd->bd->bi_dram[2].start;
548 final_map[index].phys = gd->bd->bi_dram[2].start;
549 final_map[index].size = gd->bd->bi_dram[2].size;
550#else
551 final_map[index].size = 0;
552#endif
553 break;
554#endif
555 default:
556 break;
557 }
558 }
559
560#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
561 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
562 if (el == 3) {
563
564
565
566
567
568 index = ARRAY_SIZE(final_map) - 2;
569 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
570 final_map[index].virt = gd->arch.secure_ram & ~0x3;
571 final_map[index].phys = final_map[index].virt;
572 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
573 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
574 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
575 tlb_addr_save = gd->arch.tlb_addr;
576 } else {
577
578 tlb_addr_save = gd->arch.tlb_allocated;
579 gd->arch.tlb_addr = tlb_addr_save;
580 }
581 }
582#endif
583
584
585 gd->arch.tlb_fillptr = tlb_addr_save;
586
587
588 setup_pgtables();
589
590
591 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
592 gd->arch.tlb_emerg = gd->arch.tlb_addr;
593 setup_pgtables();
594 gd->arch.tlb_addr = tlb_addr_save;
595
596
597 dcache_disable();
598 invalidate_icache_all();
599
600
601 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
602 MEMORY_ATTRIBUTES);
603
604 set_sctlr(get_sctlr() | CR_M);
605}
606
607u64 get_page_table_size(void)
608{
609 return 0x10000;
610}
611
612int arch_cpu_init(void)
613{
614
615
616
617
618
619 if (get_sctlr() & CR_M)
620 return 0;
621
622 icache_enable();
623 __asm_invalidate_dcache_all();
624 __asm_invalidate_tlb_all();
625 early_mmu_setup();
626 set_sctlr(get_sctlr() | CR_C);
627 return 0;
628}
629
630void mmu_setup(void)
631{
632 final_mmu_setup();
633}
634
635
636
637
638
639void enable_caches(void)
640{
641 mmu_setup();
642 __asm_invalidate_tlb_all();
643 icache_enable();
644 dcache_enable();
645}
646#endif
647
648#ifdef CONFIG_TFABOOT
649enum boot_src __get_boot_src(u32 porsr1)
650{
651 enum boot_src src = BOOT_SOURCE_RESERVED;
652 u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
653#if !defined(CONFIG_NXP_LSCH3_2)
654 u32 val;
655#endif
656 debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
657
658#if defined(CONFIG_FSL_LSCH3)
659#if defined(CONFIG_NXP_LSCH3_2)
660 switch (rcw_src) {
661 case RCW_SRC_SDHC1_VAL:
662 src = BOOT_SOURCE_SD_MMC;
663 break;
664 case RCW_SRC_SDHC2_VAL:
665 src = BOOT_SOURCE_SD_MMC2;
666 break;
667 case RCW_SRC_I2C1_VAL:
668 src = BOOT_SOURCE_I2C1_EXTENDED;
669 break;
670 case RCW_SRC_FLEXSPI_NAND2K_VAL:
671 src = BOOT_SOURCE_XSPI_NAND;
672 break;
673 case RCW_SRC_FLEXSPI_NAND4K_VAL:
674 src = BOOT_SOURCE_XSPI_NAND;
675 break;
676 case RCW_SRC_RESERVED_1_VAL:
677 src = BOOT_SOURCE_RESERVED;
678 break;
679 case RCW_SRC_FLEXSPI_NOR_24B:
680 src = BOOT_SOURCE_XSPI_NOR;
681 break;
682 default:
683 src = BOOT_SOURCE_RESERVED;
684 }
685#else
686 val = rcw_src & RCW_SRC_TYPE_MASK;
687 if (val == RCW_SRC_NOR_VAL) {
688 val = rcw_src & NOR_TYPE_MASK;
689
690 switch (val) {
691 case NOR_16B_VAL:
692 case NOR_32B_VAL:
693 src = BOOT_SOURCE_IFC_NOR;
694 break;
695 default:
696 src = BOOT_SOURCE_RESERVED;
697 }
698 } else {
699
700 val = rcw_src & RCW_SRC_SERIAL_MASK;
701 switch (val) {
702 case RCW_SRC_QSPI_VAL:
703
704 src = BOOT_SOURCE_QSPI_NOR;
705 break;
706 case RCW_SRC_SD_CARD_VAL:
707
708 src = BOOT_SOURCE_SD_MMC;
709 break;
710 case RCW_SRC_EMMC_VAL:
711
712 src = BOOT_SOURCE_SD_MMC;
713 break;
714 case RCW_SRC_I2C1_VAL:
715
716 src = BOOT_SOURCE_I2C1_EXTENDED;
717 break;
718 default:
719 src = BOOT_SOURCE_RESERVED;
720 }
721 }
722#endif
723#elif defined(CONFIG_FSL_LSCH2)
724
725 val = rcw_src & RCW_SRC_NAND_MASK;
726 if (val == RCW_SRC_NAND_VAL) {
727 val = rcw_src & NAND_RESERVED_MASK;
728 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
729 src = BOOT_SOURCE_IFC_NAND;
730
731 } else {
732
733 val = rcw_src & RCW_SRC_NOR_MASK;
734 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
735 src = BOOT_SOURCE_IFC_NOR;
736 } else {
737 switch (rcw_src) {
738 case QSPI_VAL1:
739 case QSPI_VAL2:
740 src = BOOT_SOURCE_QSPI_NOR;
741 break;
742 case SD_VAL:
743 src = BOOT_SOURCE_SD_MMC;
744 break;
745 default:
746 src = BOOT_SOURCE_RESERVED;
747 }
748 }
749 }
750#endif
751
752 if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
753 src = BOOT_SOURCE_QSPI_NOR;
754
755 debug("%s: src 0x%x\n", __func__, src);
756 return src;
757}
758
759enum boot_src get_boot_src(void)
760{
761 struct pt_regs regs;
762 u32 porsr1 = 0;
763
764#if defined(CONFIG_FSL_LSCH3)
765 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
766#elif defined(CONFIG_FSL_LSCH2)
767 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
768#endif
769
770 if (current_el() == 2) {
771 regs.regs[0] = SIP_SVC_RCW;
772
773 smc_call(®s);
774 if (!regs.regs[0])
775 porsr1 = regs.regs[1];
776 }
777
778 if (current_el() == 3 || !porsr1) {
779#ifdef CONFIG_FSL_LSCH3
780 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
781#elif defined(CONFIG_FSL_LSCH2)
782 porsr1 = in_be32(&gur->porsr1);
783#endif
784 }
785
786 debug("%s: porsr1 0x%x\n", __func__, porsr1);
787
788 return __get_boot_src(porsr1);
789}
790
791#ifdef CONFIG_ENV_IS_IN_MMC
792int mmc_get_env_dev(void)
793{
794 enum boot_src src = get_boot_src();
795 int dev = CONFIG_SYS_MMC_ENV_DEV;
796
797 switch (src) {
798 case BOOT_SOURCE_SD_MMC:
799 dev = 0;
800 break;
801 case BOOT_SOURCE_SD_MMC2:
802 dev = 1;
803 break;
804 default:
805 break;
806 }
807
808 return dev;
809}
810#endif
811
812enum env_location env_get_location(enum env_operation op, int prio)
813{
814 enum boot_src src = get_boot_src();
815 enum env_location env_loc = ENVL_NOWHERE;
816
817 if (prio)
818 return ENVL_UNKNOWN;
819
820#ifdef CONFIG_ENV_IS_NOWHERE
821 return env_loc;
822#endif
823
824 switch (src) {
825 case BOOT_SOURCE_IFC_NOR:
826 env_loc = ENVL_FLASH;
827 break;
828 case BOOT_SOURCE_QSPI_NOR:
829
830 case BOOT_SOURCE_XSPI_NOR:
831 env_loc = ENVL_SPI_FLASH;
832 break;
833 case BOOT_SOURCE_IFC_NAND:
834
835 case BOOT_SOURCE_QSPI_NAND:
836
837 case BOOT_SOURCE_XSPI_NAND:
838 env_loc = ENVL_NAND;
839 break;
840 case BOOT_SOURCE_SD_MMC:
841
842 case BOOT_SOURCE_SD_MMC2:
843 env_loc = ENVL_MMC;
844 break;
845 case BOOT_SOURCE_I2C1_EXTENDED:
846
847 default:
848 break;
849 }
850
851 return env_loc;
852}
853#endif
854
855u32 initiator_type(u32 cluster, int init_id)
856{
857 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
858 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
859 u32 type = 0;
860
861 type = gur_in32(&gur->tp_ityp[idx]);
862 if (type & TP_ITYP_AV)
863 return type;
864
865 return 0;
866}
867
868u32 cpu_pos_mask(void)
869{
870 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
871 int i = 0;
872 u32 cluster, type, mask = 0;
873
874 do {
875 int j;
876
877 cluster = gur_in32(&gur->tp_cluster[i].lower);
878 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
879 type = initiator_type(cluster, j);
880 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
881 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
882 }
883 i++;
884 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
885
886 return mask;
887}
888
889u32 cpu_mask(void)
890{
891 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
892 int i = 0, count = 0;
893 u32 cluster, type, mask = 0;
894
895 do {
896 int j;
897
898 cluster = gur_in32(&gur->tp_cluster[i].lower);
899 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
900 type = initiator_type(cluster, j);
901 if (type) {
902 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
903 mask |= 1 << count;
904 count++;
905 }
906 }
907 i++;
908 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
909
910 return mask;
911}
912
913
914
915
916int cpu_numcores(void)
917{
918 return hweight32(cpu_mask());
919}
920
921int fsl_qoriq_core_to_cluster(unsigned int core)
922{
923 struct ccsr_gur __iomem *gur =
924 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
925 int i = 0, count = 0;
926 u32 cluster;
927
928 do {
929 int j;
930
931 cluster = gur_in32(&gur->tp_cluster[i].lower);
932 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
933 if (initiator_type(cluster, j)) {
934 if (count == core)
935 return i;
936 count++;
937 }
938 }
939 i++;
940 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
941
942 return -1;
943}
944
945u32 fsl_qoriq_core_to_type(unsigned int core)
946{
947 struct ccsr_gur __iomem *gur =
948 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
949 int i = 0, count = 0;
950 u32 cluster, type;
951
952 do {
953 int j;
954
955 cluster = gur_in32(&gur->tp_cluster[i].lower);
956 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
957 type = initiator_type(cluster, j);
958 if (type) {
959 if (count == core)
960 return type;
961 count++;
962 }
963 }
964 i++;
965 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
966
967 return -1;
968}
969
970#ifndef CONFIG_FSL_LSCH3
971uint get_svr(void)
972{
973 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
974
975 return gur_in32(&gur->svr);
976}
977#endif
978
979#ifdef CONFIG_DISPLAY_CPUINFO
980int print_cpuinfo(void)
981{
982 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
983 struct sys_info sysinfo;
984 char buf[32];
985 unsigned int i, core;
986 u32 type, rcw, svr = gur_in32(&gur->svr);
987
988 puts("SoC: ");
989
990 cpu_name(buf);
991 printf(" %s (0x%x)\n", buf, svr);
992 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
993 get_sys_info(&sysinfo);
994 puts("Clock Configuration:");
995 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
996 if (!(i % 3))
997 puts("\n ");
998 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
999 printf("CPU%d(%s):%-4s MHz ", core,
1000 type == TY_ITYP_VER_A7 ? "A7 " :
1001 (type == TY_ITYP_VER_A53 ? "A53" :
1002 (type == TY_ITYP_VER_A57 ? "A57" :
1003 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
1004 strmhz(buf, sysinfo.freq_processor[core]));
1005 }
1006
1007 printf("\n Bus: %-4s MHz ",
1008 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1009 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1010#ifdef CONFIG_SYS_DPAA_FMAN
1011 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1012#endif
1013#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1014 if (soc_has_dp_ddr()) {
1015 printf(" DP-DDR: %-4s MT/s",
1016 strmhz(buf, sysinfo.freq_ddrbus2));
1017 }
1018#endif
1019 puts("\n");
1020
1021
1022
1023
1024
1025 puts("Reset Configuration Word (RCW):");
1026 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1027 rcw = gur_in32(&gur->rcwsr[i]);
1028 if ((i % 4) == 0)
1029 printf("\n %08x:", i * 4);
1030 printf(" %08x", rcw);
1031 }
1032 puts("\n");
1033
1034 return 0;
1035}
1036#endif
1037
1038#ifdef CONFIG_FSL_ESDHC
1039int cpu_mmc_init(bd_t *bis)
1040{
1041 return fsl_esdhc_mmc_init(bis);
1042}
1043#endif
1044
1045int cpu_eth_init(bd_t *bis)
1046{
1047 int error = 0;
1048
1049#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1050 error = fsl_mc_ldpaa_init(bis);
1051#endif
1052#ifdef CONFIG_FMAN_ENET
1053 fm_standard_init(bis);
1054#endif
1055 return error;
1056}
1057
1058static inline int check_psci(void)
1059{
1060 unsigned int psci_ver;
1061
1062 psci_ver = sec_firmware_support_psci_version();
1063 if (psci_ver == PSCI_INVALID_VER)
1064 return 1;
1065
1066 return 0;
1067}
1068
1069static void config_core_prefetch(void)
1070{
1071 char *buf = NULL;
1072 char buffer[HWCONFIG_BUFFER_SIZE];
1073 const char *prefetch_arg = NULL;
1074 size_t arglen;
1075 unsigned int mask;
1076 struct pt_regs regs;
1077
1078 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1079 buf = buffer;
1080 else
1081 return;
1082
1083 prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1084 &arglen, buf);
1085
1086 if (prefetch_arg) {
1087 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1088 if (mask & 0x1) {
1089 printf("Core0 prefetch can't be disabled\n");
1090 return;
1091 }
1092
1093#define SIP_PREFETCH_DISABLE_64 0xC200FF13
1094 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1095 regs.regs[1] = mask;
1096 smc_call(®s);
1097
1098 if (regs.regs[0])
1099 printf("Prefetch disable config failed for mask ");
1100 else
1101 printf("Prefetch disable config passed for mask ");
1102 printf("0x%x\n", mask);
1103 }
1104}
1105
1106#ifdef CONFIG_PCIE_ECAM_GENERIC
1107__weak void set_ecam_icids(void)
1108{
1109}
1110#endif
1111
1112int arch_early_init_r(void)
1113{
1114#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1115 u32 svr_dev_id;
1116
1117
1118
1119
1120 svr_dev_id = get_svr();
1121 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1122 erratum_a009635();
1123#endif
1124#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1125 erratum_a009942_check_cpo();
1126#endif
1127 if (check_psci()) {
1128 debug("PSCI: PSCI does not exist.\n");
1129
1130
1131 if (fsl_layerscape_wake_seconday_cores())
1132 printf("Did not wake secondary cores\n");
1133 }
1134
1135 config_core_prefetch();
1136
1137#ifdef CONFIG_SYS_HAS_SERDES
1138 fsl_serdes_init();
1139#endif
1140#ifdef CONFIG_SYS_FSL_HAS_RGMII
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156 fsl_rgmii_init();
1157#endif
1158#ifdef CONFIG_FMAN_ENET
1159 fman_enet_init();
1160#endif
1161#ifdef CONFIG_SYS_DPAA_QBMAN
1162 setup_qbman_portals();
1163#endif
1164#ifdef CONFIG_PCIE_ECAM_GENERIC
1165 set_ecam_icids();
1166#endif
1167 return 0;
1168}
1169
1170int timer_init(void)
1171{
1172 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1173#ifdef CONFIG_FSL_LSCH3
1174 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1175#endif
1176#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1177 defined(CONFIG_ARCH_LS1028A)
1178 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1179 u32 svr_dev_id;
1180#endif
1181#ifdef COUNTER_FREQUENCY_REAL
1182 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1183
1184
1185 if (current_el() == 3)
1186 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1187#endif
1188
1189#ifdef CONFIG_FSL_LSCH3
1190
1191
1192
1193 out_le32(cltbenr, 0xf);
1194#endif
1195
1196#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1197 defined(CONFIG_ARCH_LS1028A)
1198
1199
1200
1201
1202
1203 setbits_le32(pctbenr, 0xff);
1204
1205
1206
1207
1208 svr_dev_id = get_svr();
1209 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1210 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1211
1212#endif
1213
1214
1215
1216
1217 out_le32(cntcr, 0x1);
1218
1219 return 0;
1220}
1221
1222__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1223
1224void __efi_runtime reset_cpu(ulong addr)
1225{
1226 u32 val;
1227
1228#ifdef CONFIG_ARCH_LX2160A
1229 val = in_le32(rstcr);
1230 val |= 0x01;
1231 out_le32(rstcr, val);
1232#else
1233
1234 val = scfg_in32(rstcr);
1235 val |= 0x02;
1236 scfg_out32(rstcr, val);
1237#endif
1238}
1239
1240#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1241
1242void __efi_runtime EFIAPI efi_reset_system(
1243 enum efi_reset_type reset_type,
1244 efi_status_t reset_status,
1245 unsigned long data_size, void *reset_data)
1246{
1247 switch (reset_type) {
1248 case EFI_RESET_COLD:
1249 case EFI_RESET_WARM:
1250 case EFI_RESET_PLATFORM_SPECIFIC:
1251 reset_cpu(0);
1252 break;
1253 case EFI_RESET_SHUTDOWN:
1254
1255 break;
1256 }
1257
1258 while (1) { }
1259}
1260
1261efi_status_t efi_reset_system_init(void)
1262{
1263 return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1264}
1265
1266#endif
1267
1268
1269
1270
1271
1272
1273phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1274{
1275 phys_size_t ram_top = ram_size;
1276
1277#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1278 ram_top = mc_get_dram_block_size();
1279 if (ram_top > ram_size)
1280 return ram_size + ram_top;
1281
1282 ram_top = ram_size - ram_top;
1283
1284 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1285#endif
1286
1287 return ram_size - ram_top;
1288}
1289
1290phys_size_t get_effective_memsize(void)
1291{
1292 phys_size_t ea_size, rem = 0;
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1306 ea_size = CONFIG_MAX_MEM_MAPPED;
1307 rem = gd->ram_size - ea_size;
1308 } else {
1309 ea_size = gd->ram_size;
1310 }
1311
1312#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1313
1314 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1315 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1316 else
1317 printf("Error: No enough space for secure memory.\n");
1318#endif
1319
1320 if (rem < board_reserve_ram_top(rem)) {
1321
1322 if (ea_size > board_reserve_ram_top(ea_size))
1323 ea_size -= board_reserve_ram_top(ea_size);
1324 else
1325 printf("Error: No enough space for reserved memory.\n");
1326 }
1327
1328 return ea_size;
1329}
1330
1331#ifdef CONFIG_TFABOOT
1332phys_size_t tfa_get_dram_size(void)
1333{
1334 struct pt_regs regs;
1335 phys_size_t dram_size = 0;
1336
1337 regs.regs[0] = SMC_DRAM_BANK_INFO;
1338 regs.regs[1] = -1;
1339
1340 smc_call(®s);
1341 if (regs.regs[0])
1342 return 0;
1343
1344 dram_size = regs.regs[1];
1345 return dram_size;
1346}
1347
1348static int tfa_dram_init_banksize(void)
1349{
1350 int i = 0, ret = 0;
1351 struct pt_regs regs;
1352 phys_size_t dram_size = tfa_get_dram_size();
1353
1354 debug("dram_size %llx\n", dram_size);
1355
1356 if (!dram_size)
1357 return -EINVAL;
1358
1359 do {
1360 regs.regs[0] = SMC_DRAM_BANK_INFO;
1361 regs.regs[1] = i;
1362
1363 smc_call(®s);
1364 if (regs.regs[0]) {
1365 ret = -EINVAL;
1366 break;
1367 }
1368
1369 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1370 regs.regs[2]);
1371 gd->bd->bi_dram[i].start = regs.regs[1];
1372 gd->bd->bi_dram[i].size = regs.regs[2];
1373
1374 dram_size -= gd->bd->bi_dram[i].size;
1375
1376 i++;
1377 } while (dram_size);
1378
1379 if (i > 0)
1380 ret = 0;
1381
1382#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1383
1384#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1385 if (gd->bd->bi_dram[2].size >=
1386 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1387 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1388 gd->bd->bi_dram[2].size -
1389 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1390 } else
1391#endif
1392 {
1393 if (gd->bd->bi_dram[1].size >=
1394 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1395 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1396 gd->bd->bi_dram[1].size -
1397 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1398 } else if (gd->bd->bi_dram[0].size >
1399 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1400 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1401 gd->bd->bi_dram[0].size -
1402 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1403 }
1404 }
1405#endif
1406
1407 return ret;
1408}
1409#endif
1410
1411int dram_init_banksize(void)
1412{
1413#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1414 phys_size_t dp_ddr_size;
1415#endif
1416
1417#ifdef CONFIG_TFABOOT
1418 if (!tfa_dram_init_banksize())
1419 return 0;
1420#endif
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1432 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1433 debug("No need to run again, skip %s\n", __func__);
1434
1435 return 0;
1436 }
1437#endif
1438
1439 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1440 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1441 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1442 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1443 gd->bd->bi_dram[1].size = gd->ram_size -
1444 CONFIG_SYS_DDR_BLOCK1_SIZE;
1445#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1446 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1447 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1448 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1449 CONFIG_SYS_DDR_BLOCK2_SIZE;
1450 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1451 }
1452#endif
1453 } else {
1454 gd->bd->bi_dram[0].size = gd->ram_size;
1455 }
1456#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1457 if (gd->bd->bi_dram[0].size >
1458 CONFIG_SYS_MEM_RESERVE_SECURE) {
1459 gd->bd->bi_dram[0].size -=
1460 CONFIG_SYS_MEM_RESERVE_SECURE;
1461 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1462 gd->bd->bi_dram[0].size;
1463 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1464 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1465 }
1466#endif
1467
1468#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1469
1470#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1471 if (gd->bd->bi_dram[2].size >=
1472 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1473 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1474 gd->bd->bi_dram[2].size -
1475 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1476 } else
1477#endif
1478 {
1479 if (gd->bd->bi_dram[1].size >=
1480 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1481 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1482 gd->bd->bi_dram[1].size -
1483 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1484 } else if (gd->bd->bi_dram[0].size >
1485 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1486 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1487 gd->bd->bi_dram[0].size -
1488 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1489 }
1490 }
1491#endif
1492
1493#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1494#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1495#error "This SoC shouldn't have DP DDR"
1496#endif
1497 if (soc_has_dp_ddr()) {
1498
1499 puts("DP-DDR: ");
1500
1501
1502
1503
1504 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1505 CONFIG_DP_DDR_CTRL,
1506 CONFIG_DP_DDR_NUM_CTRLS,
1507 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1508 NULL, NULL, NULL);
1509 if (dp_ddr_size) {
1510 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1511 gd->bd->bi_dram[2].size = dp_ddr_size;
1512 } else {
1513 puts("Not detected");
1514 }
1515 }
1516#endif
1517
1518#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1519 debug("%s is called. gd->ram_size is reduced to %lu\n",
1520 __func__, (ulong)gd->ram_size);
1521#endif
1522
1523 return 0;
1524}
1525
1526#if CONFIG_IS_ENABLED(EFI_LOADER)
1527void efi_add_known_memory(void)
1528{
1529 int i;
1530 phys_addr_t ram_start, start;
1531 phys_size_t ram_size;
1532 u64 pages;
1533
1534
1535 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1536#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1537#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1538#error "This SoC shouldn't have DP DDR"
1539#endif
1540 if (i == 2)
1541 continue;
1542#endif
1543 ram_start = gd->bd->bi_dram[i].start;
1544 ram_size = gd->bd->bi_dram[i].size;
1545#ifdef CONFIG_RESV_RAM
1546 if (gd->arch.resv_ram >= ram_start &&
1547 gd->arch.resv_ram < ram_start + ram_size)
1548 ram_size = gd->arch.resv_ram - ram_start;
1549#endif
1550 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1551 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1552
1553 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1554 false);
1555 }
1556}
1557#endif
1558
1559
1560
1561
1562
1563
1564
1565
1566void update_early_mmu_table(void)
1567{
1568 if (!gd->arch.tlb_addr)
1569 return;
1570
1571 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1572 mmu_change_region_attr(
1573 CONFIG_SYS_SDRAM_BASE,
1574 gd->ram_size,
1575 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1576 PTE_BLOCK_OUTER_SHARE |
1577 PTE_BLOCK_NS |
1578 PTE_TYPE_VALID);
1579 } else {
1580 mmu_change_region_attr(
1581 CONFIG_SYS_SDRAM_BASE,
1582 CONFIG_SYS_DDR_BLOCK1_SIZE,
1583 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1584 PTE_BLOCK_OUTER_SHARE |
1585 PTE_BLOCK_NS |
1586 PTE_TYPE_VALID);
1587#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1588#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1589#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1590#endif
1591 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1592 CONFIG_SYS_DDR_BLOCK2_SIZE) {
1593 mmu_change_region_attr(
1594 CONFIG_SYS_DDR_BLOCK2_BASE,
1595 CONFIG_SYS_DDR_BLOCK2_SIZE,
1596 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1597 PTE_BLOCK_OUTER_SHARE |
1598 PTE_BLOCK_NS |
1599 PTE_TYPE_VALID);
1600 mmu_change_region_attr(
1601 CONFIG_SYS_DDR_BLOCK3_BASE,
1602 gd->ram_size -
1603 CONFIG_SYS_DDR_BLOCK1_SIZE -
1604 CONFIG_SYS_DDR_BLOCK2_SIZE,
1605 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1606 PTE_BLOCK_OUTER_SHARE |
1607 PTE_BLOCK_NS |
1608 PTE_TYPE_VALID);
1609 } else
1610#endif
1611 {
1612 mmu_change_region_attr(
1613 CONFIG_SYS_DDR_BLOCK2_BASE,
1614 gd->ram_size -
1615 CONFIG_SYS_DDR_BLOCK1_SIZE,
1616 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1617 PTE_BLOCK_OUTER_SHARE |
1618 PTE_BLOCK_NS |
1619 PTE_TYPE_VALID);
1620 }
1621 }
1622}
1623
1624__weak int dram_init(void)
1625{
1626 fsl_initdram();
1627#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1628 defined(CONFIG_SPL_BUILD)
1629
1630 update_early_mmu_table();
1631#endif
1632
1633 return 0;
1634}
1635
1636#ifdef CONFIG_ARCH_MISC_INIT
1637__weak int serdes_misc_init(void)
1638{
1639 return 0;
1640}
1641
1642int arch_misc_init(void)
1643{
1644 serdes_misc_init();
1645
1646 return 0;
1647}
1648#endif
1649