LXR uboot/arch/arm/include/asm/arch-sunxi/dma

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
   4 */
   5
   6#ifndef _SUNXI_DMA_SUN4I_H
   7#define _SUNXI_DMA_SUN4I_H
   8
   9struct sunxi_dma_cfg
  10{
  11        u32 ctl;                /* 0x00 Control */
  12        u32 src_addr;           /* 0x04 Source address */
  13        u32 dst_addr;           /* 0x08 Destination address */
  14        u32 bc;                 /* 0x0C Byte counter */
  15        u32 res0[2];
  16        u32 ddma_para;          /* 0x18 extra parameter (dedicated DMA only) */
  17        u32 res1;
  18};
  19
  20struct sunxi_dma
  21{
  22        u32 irq_en;                     /* 0x000 IRQ enable */
  23        u32 irq_pend;                   /* 0x004 IRQ pending */
  24        u32 auto_gate;                  /* 0x008 auto gating */
  25        u32 res0[61];
  26        struct sunxi_dma_cfg ndma[8];   /* 0x100 Normal DMA */
  27        u32 res1[64];
  28        struct sunxi_dma_cfg ddma[8];   /* 0x300 Dedicated DMA */
  29};
  30
  31enum ddma_drq_type {
  32        DDMA_DST_DRQ_SRAM = 0,
  33        DDMA_SRC_DRQ_SRAM = 0,
  34        DDMA_DST_DRQ_SDRAM = 1,
  35        DDMA_SRC_DRQ_SDRAM = 1,
  36        DDMA_DST_DRQ_PATA = 2,
  37        DDMA_SRC_DRQ_PATA = 2,
  38        DDMA_DST_DRQ_NAND = 3,
  39        DDMA_SRC_DRQ_NAND = 3,
  40        DDMA_DST_DRQ_USB0 = 4,
  41        DDMA_SRC_DRQ_USB0 = 4,
  42        DDMA_DST_DRQ_ETHERNET_MAC_TX = 6,
  43        DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7,
  44        DDMA_DST_DRQ_SPI1_TX = 8,
  45        DDMA_SRC_DRQ_SPI1_RX = 9,
  46        DDMA_DST_DRQ_SECURITY_SYS_TX = 10,
  47        DDMA_SRC_DRQ_SECURITY_SYS_RX = 11,
  48        DDMA_DST_DRQ_TCON0 = 14,
  49        DDMA_DST_DRQ_TCON1 = 15,
  50        DDMA_DST_DRQ_MSC = 23,
  51        DDMA_SRC_DRQ_MSC = 23,
  52        DDMA_DST_DRQ_SPI0_TX = 26,
  53        DDMA_SRC_DRQ_SPI0_RX = 27,
  54        DDMA_DST_DRQ_SPI2_TX = 28,
  55        DDMA_SRC_DRQ_SPI2_RX = 29,
  56        DDMA_DST_DRQ_SPI3_TX = 30,
  57        DDMA_SRC_DRQ_SPI3_RX = 31,
  58};
  59
  60#define SUNXI_DMA_CTL_SRC_DRQ(a)                ((a) & 0x1f)
  61#define SUNXI_DMA_CTL_MODE_IO                   (1 << 5)
  62#define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32         (2 << 9)
  63#define SUNXI_DMA_CTL_DST_DRQ(a)                (((a) & 0x1f) << 16)
  64#define SUNXI_DMA_CTL_DST_DATA_WIDTH_32         (2 << 25)
  65#define SUNXI_DMA_CTL_TRIGGER                   (1 << 31)
  66
  67#endif /* _SUNXI_DMA_SUN4I_H */
  68