LXR uboot/arch/m68k/include/asm/immap

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * MCF5282 Internal Memory Map
   4 *
   5 * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   6 */
   7
   8#ifndef __IMMAP_5282__
   9#define __IMMAP_5282__
  10
  11#define MMAP_SCM        (CONFIG_SYS_MBAR + 0x00000000)
  12#define MMAP_SDRAMC     (CONFIG_SYS_MBAR + 0x00000040)
  13#define MMAP_FBCS       (CONFIG_SYS_MBAR + 0x00000080)
  14#define MMAP_DMA0       (CONFIG_SYS_MBAR + 0x00000100)
  15#define MMAP_DMA1       (CONFIG_SYS_MBAR + 0x00000140)
  16#define MMAP_DMA2       (CONFIG_SYS_MBAR + 0x00000180)
  17#define MMAP_DMA3       (CONFIG_SYS_MBAR + 0x000001C0)
  18#define MMAP_UART0      (CONFIG_SYS_MBAR + 0x00000200)
  19#define MMAP_UART1      (CONFIG_SYS_MBAR + 0x00000240)
  20#define MMAP_UART2      (CONFIG_SYS_MBAR + 0x00000280)
  21#define MMAP_I2C        (CONFIG_SYS_MBAR + 0x00000300)
  22#define MMAP_QSPI       (CONFIG_SYS_MBAR + 0x00000340)
  23#define MMAP_DTMR0      (CONFIG_SYS_MBAR + 0x00000400)
  24#define MMAP_DTMR1      (CONFIG_SYS_MBAR + 0x00000440)
  25#define MMAP_DTMR2      (CONFIG_SYS_MBAR + 0x00000480)
  26#define MMAP_DTMR3      (CONFIG_SYS_MBAR + 0x000004C0)
  27#define MMAP_INTC0      (CONFIG_SYS_MBAR + 0x00000C00)
  28#define MMAP_INTC1      (CONFIG_SYS_MBAR + 0x00000D00)
  29#define MMAP_INTCACK    (CONFIG_SYS_MBAR + 0x00000F00)
  30#define MMAP_FEC        (CONFIG_SYS_MBAR + 0x00001000)
  31#define MMAP_FECFIFO    (CONFIG_SYS_MBAR + 0x00001400)
  32#define MMAP_GPIO       (CONFIG_SYS_MBAR + 0x00100000)
  33#define MMAP_CCM        (CONFIG_SYS_MBAR + 0x00110000)
  34#define MMAP_PLL        (CONFIG_SYS_MBAR + 0x00120000)
  35#define MMAP_EPORT      (CONFIG_SYS_MBAR + 0x00130000)
  36#define MMAP_WDOG       (CONFIG_SYS_MBAR + 0x00140000)
  37#define MMAP_PIT0       (CONFIG_SYS_MBAR + 0x00150000)
  38#define MMAP_PIT1       (CONFIG_SYS_MBAR + 0x00160000)
  39#define MMAP_PIT2       (CONFIG_SYS_MBAR + 0x00170000)
  40#define MMAP_PIT3       (CONFIG_SYS_MBAR + 0x00180000)
  41#define MMAP_QADC       (CONFIG_SYS_MBAR + 0x00190000)
  42#define MMAP_GPTMRA     (CONFIG_SYS_MBAR + 0x001A0000)
  43#define MMAP_GPTMRB     (CONFIG_SYS_MBAR + 0x001B0000)
  44#define MMAP_CAN        (CONFIG_SYS_MBAR + 0x001C0000)
  45#define MMAP_CFMC       (CONFIG_SYS_MBAR + 0x001D0000)
  46#define MMAP_CFMMEM     (CONFIG_SYS_MBAR + 0x04000000)
  47
  48#include <asm/coldfire/eport.h>
  49#include <asm/coldfire/flexbus.h>
  50#include <asm/coldfire/flexcan.h>
  51#include <asm/coldfire/intctrl.h>
  52#include <asm/coldfire/qspi.h>
  53
  54/* System Control Module */
  55typedef struct scm_ctrl {
  56        u32 ipsbar;
  57        u32 res1;
  58        u32 rambar;
  59        u32 res2;
  60        u8 crsr;
  61        u8 cwcr;
  62        u8 lpicr;
  63        u8 cwsr;
  64        u32 res3;
  65        u8 mpark;
  66        u8 res4[3];
  67        u8 pacr0;
  68        u8 pacr1;
  69        u8 pacr2;
  70        u8 pacr3;
  71        u8 pacr4;
  72        u8 res5;
  73        u8 pacr5;
  74        u8 pacr6;
  75        u8 pacr7;
  76        u8 res6;
  77        u8 pacr8;
  78        u8 res7;
  79        u8 gpacr0;
  80        u8 gpacr1;
  81        u16 res8;
  82} scm_t;
  83
  84typedef struct canex_ctrl {
  85        can_msg_t msg[16];      /* 0x00 Message Buffer 0-15 */
  86} canex_t;
  87
  88/* Clock Module registers */
  89typedef struct pll_ctrl {
  90        u16 syncr;              /* 0x00 synthesizer control register */
  91        u16 synsr;              /* 0x02 synthesizer status register */
  92} pll_t;
  93
  94/* Watchdog registers */
  95typedef struct wdog_ctrl {
  96        ushort wcr;
  97        ushort wmr;
  98        ushort wcntr;
  99        ushort wsr;
 100} wdog_t;
 101
 102#endif                          /* __IMMAP_5282__ */
 103