LXR uboot/arch/powerpc/cpu/mpc85xx/fsl_corenet

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2009-2010 Freescale Semiconductor, Inc.
   4 *
   5 * Author: Roy Zang <tie-fei.zang@freescale.com>
   6 */
   7
   8#ifndef __FSL_CORENET_SERDES_H
   9#define __FSL_CORENET_SERDES_H
  10
  11enum srds_bank {
  12        FSL_SRDS_BANK_1  = 0,
  13        FSL_SRDS_BANK_2  = 1,
  14        FSL_SRDS_BANK_3  = 2,
  15};
  16
  17int is_serdes_prtcl_valid(u32 prtcl);
  18int serdes_get_lane_idx(int lane);
  19int serdes_get_bank_by_lane(int lane);
  20int serdes_lane_enabled(int lane);
  21enum srds_prtcl serdes_get_prtcl(int cfg, int lane);
  22
  23#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  24extern uint16_t srds_lpd_b[SRDS_MAX_BANK];
  25#endif
  26
  27#endif /* __FSL_CORENET_SERDES_H */
  28