1
2
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4
5
6#include <common.h>
7#include <asm/fsl_serdes.h>
8#include <asm/processor.h>
9#include <asm/io.h>
10#include "fsl_corenet2_serdes.h"
11
12struct serdes_config {
13 u32 protocol;
14 u8 lanes[SRDS_MAX_LANES];
15};
16
17#ifdef CONFIG_ARCH_T4240
18static const struct serdes_config serdes1_cfg_tbl[] = {
19
20 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
21 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
22 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
23 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
24 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
25 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
26 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
27 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
28 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
29 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
30 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
31 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
32 {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
33 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
34 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
35 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
36 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
37 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
38 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
39 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
40 {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
41 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
42 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
43 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
44 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
45 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
46 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
47 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
48 {37, {NONE, NONE, QSGMII_FM1_B, NONE,
49 NONE, NONE, QSGMII_FM1_A, NONE} },
50 {38, {NONE, NONE, QSGMII_FM1_B, NONE,
51 NONE, NONE, QSGMII_FM1_A, NONE}},
52 {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
53 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
54 NONE, NONE, QSGMII_FM1_A, NONE} },
55 {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
56 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
57 NONE, NONE, QSGMII_FM1_A, NONE}},
58 {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
59 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
60 NONE, NONE, QSGMII_FM1_A, NONE} },
61 {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
62 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
63 NONE, NONE, QSGMII_FM1_A, NONE}},
64 {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
65 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
66 NONE, NONE, QSGMII_FM1_A, NONE} },
67 {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
68 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
69 NONE, NONE, QSGMII_FM1_A, NONE}},
70 {}
71};
72static const struct serdes_config serdes2_cfg_tbl[] = {
73
74 {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
75 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
76 XAUI_FM2_MAC10, XAUI_FM2_MAC10,
77 XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
78 {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
79 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
80 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
81 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
82 {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
83 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
84 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
85 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
86 {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
87 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
88 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
89 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
90 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
91 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
92 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
93 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
94 {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
95 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
96 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
97 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
98 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
99 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
100 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
101 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
102 {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
103 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
104 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
105 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
106 {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
107 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
108 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
109 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
110 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
111 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
112 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
113 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
114 {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
115 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
116 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
117 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
118 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
119 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
120 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
121 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
122 {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
123 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
124 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
125 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
126 {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
127 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
128 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
129 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
130 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
131 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
132 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
133 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
134 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
135 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
136 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
137 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
138 {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
139 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
140 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
141 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
142 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
143 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
144 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
145 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
146 {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
147 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
148 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
149 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
150 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
151 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
152 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
153 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
154 {37, {NONE, NONE, QSGMII_FM2_B, NONE,
155 NONE, NONE, QSGMII_FM2_A, NONE} },
156 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
157 NONE, NONE, QSGMII_FM2_A, NONE} },
158 {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
159 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
160 NONE, NONE, QSGMII_FM2_A, NONE} },
161 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
162 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
163 NONE, NONE, QSGMII_FM2_A, NONE} },
164 {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
165 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
166 NONE, NONE, QSGMII_FM2_A, NONE} },
167 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
168 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
169 NONE, NONE, QSGMII_FM2_A, NONE} },
170 {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
171 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
172 NONE, NONE, QSGMII_FM2_A, NONE} },
173 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
174 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
175 NONE, NONE, QSGMII_FM2_A, NONE} },
176 {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
177 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
178 NONE, NONE, QSGMII_FM2_A, NONE} },
179 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
180 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
181 NONE, NONE, QSGMII_FM2_A, NONE} },
182 {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
183 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
184 NONE, NONE, QSGMII_FM2_A, NONE} },
185 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
186 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
187 NONE, NONE, QSGMII_FM2_A, NONE} },
188 {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
189 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
190 NONE, NONE, QSGMII_FM2_A, NONE} },
191 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
192 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
193 NONE, NONE, QSGMII_FM2_A, NONE} },
194 {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
195 XFI_FM2_MAC10, XFI_FM2_MAC9,
196 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
197 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
198 {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
199 XFI_FM2_MAC10, XFI_FM2_MAC9,
200 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
201 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
202 {57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
203 XFI_FM2_MAC10, XFI_FM2_MAC9,
204 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
205 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
206 {}
207};
208static const struct serdes_config serdes3_cfg_tbl[] = {
209
210 {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
211 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
212 {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
213 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
214 {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
215 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
216 {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
217 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
218 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
219 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
220 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
221 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
222 {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
223 PCIE2, PCIE2, PCIE2, PCIE2} },
224 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
225 PCIE2, PCIE2, PCIE2, PCIE2}},
226 {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
227 PCIE2, PCIE2, PCIE2, PCIE2} },
228 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
229 PCIE2, PCIE2, PCIE2, PCIE2}},
230 {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
231 SRIO1, SRIO1, SRIO1, SRIO1} },
232 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
233 SRIO1, SRIO1, SRIO1, SRIO1}},
234 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
235 SRIO1, SRIO1, SRIO1, SRIO1}},
236 {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
237 SRIO1, SRIO1, SRIO1, SRIO1} },
238 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
239 SRIO1, SRIO1, SRIO1, SRIO1}},
240 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
241 SRIO1, SRIO1, SRIO1, SRIO1}},
242 {}
243};
244static const struct serdes_config serdes4_cfg_tbl[] = {
245
246 {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
247 {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
248 {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
249 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
250 {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
251 {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
252 {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
253 {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
254 {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
255 {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
256 {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
257 {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
258 {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
259 {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
260 {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
261 {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
262 {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
263 {}
264};
265#elif defined(CONFIG_ARCH_T4160)
266static const struct serdes_config serdes1_cfg_tbl[] = {
267
268 {1, {NONE, NONE, NONE, NONE,
269 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
270 XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
271 {2, {NONE, NONE, NONE, NONE,
272 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
273 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
274 {4, {NONE, NONE, NONE, NONE,
275 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
276 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
277 {27, {NONE, NONE, NONE, NONE,
278 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
279 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
280 {28, {NONE, NONE, NONE, NONE,
281 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
282 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
283 {35, {NONE, NONE, NONE, NONE,
284 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
285 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
286 {36, {NONE, NONE, NONE, NONE,
287 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
288 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
289 {37, {NONE, NONE, NONE, NONE,
290 NONE, NONE, QSGMII_FM1_A, NONE} },
291 {38, {NONE, NONE, NONE, NONE,
292 NONE, NONE, QSGMII_FM1_A, NONE} },
293 {}
294};
295static const struct serdes_config serdes2_cfg_tbl[] = {
296
297 {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
298 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
299 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
300 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
301 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
302 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
303 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
304 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
305 {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
306 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
307 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
308 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
309 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
310 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
311 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
312 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
313 {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
314 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
315 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
316 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
317 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
318 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
319 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
320 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
321 {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
322 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
323 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
324 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
325 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
326 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
327 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
328 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
329 {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
330 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
331 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
332 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
333 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
334 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
335 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
336 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
337 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
338 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
339 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
340 NONE, NONE} },
341 {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
342 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
343 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
344 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
345 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
346 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
347 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
348 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
349 {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
350 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
351 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
352 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
353 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
354 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
355 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
356 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
357 {37, {NONE, NONE, QSGMII_FM2_B, NONE,
358 NONE, NONE, QSGMII_FM2_A, NONE} },
359 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
360 NONE, NONE, QSGMII_FM2_A, NONE} },
361 {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
362 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
363 NONE, NONE, QSGMII_FM2_A, NONE} },
364 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
365 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
366 NONE, NONE, QSGMII_FM2_A, NONE} },
367 {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
368 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
369 NONE, NONE, QSGMII_FM2_A, NONE} },
370 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
371 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
372 NONE, NONE, QSGMII_FM2_A, NONE} },
373 {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
374 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
375 NONE, NONE, QSGMII_FM2_A, NONE} },
376 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
377 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
378 NONE, NONE, QSGMII_FM2_A, NONE} },
379 {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
380 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
381 NONE, NONE, QSGMII_FM2_A, NONE} },
382 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
383 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
384 NONE, NONE, QSGMII_FM2_A, NONE} },
385 {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
386 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
387 NONE, NONE, QSGMII_FM2_A, NONE} },
388 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
389 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
390 NONE, NONE, QSGMII_FM2_A, NONE} },
391 {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
392 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
393 NONE, NONE, QSGMII_FM2_A, NONE} },
394 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
395 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
396 NONE, NONE, QSGMII_FM2_A, NONE} },
397 {55, {NONE, XFI_FM1_MAC10,
398 XFI_FM2_MAC10, NONE,
399 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
400 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
401 {56, {NONE, XFI_FM1_MAC10,
402 XFI_FM2_MAC10, NONE,
403 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
404 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
405 {57, {NONE, XFI_FM1_MAC10,
406 XFI_FM2_MAC10, NONE,
407 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
408 NONE, NONE} },
409 {}
410};
411static const struct serdes_config serdes3_cfg_tbl[] = {
412
413 {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
414 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
415 {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
416 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
417 {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
418 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
419 {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
420 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
421 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
422 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
423 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
424 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
425 {11, {NONE, NONE, NONE, NONE,
426 PCIE2, PCIE2, PCIE2, PCIE2} },
427 {12, {NONE, NONE, NONE, NONE,
428 PCIE2, PCIE2, PCIE2, PCIE2} },
429 {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
430 PCIE2, PCIE2, PCIE2, PCIE2} },
431 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
432 PCIE2, PCIE2, PCIE2, PCIE2} },
433 {15, {NONE, NONE, NONE, NONE,
434 SRIO1, SRIO1, SRIO1, SRIO1} },
435 {16, {NONE, NONE, NONE, NONE,
436 SRIO1, SRIO1, SRIO1, SRIO1} },
437 {17, {NONE, NONE, NONE, NONE,
438 SRIO1, SRIO1, SRIO1, SRIO1} },
439 {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
440 SRIO1, SRIO1, SRIO1, SRIO1} },
441 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
442 SRIO1, SRIO1, SRIO1, SRIO1} },
443 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
444 SRIO1, SRIO1, SRIO1, SRIO1} },
445 {}
446};
447static const struct serdes_config serdes4_cfg_tbl[] = {
448
449 {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
450 {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
451 {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
452 {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
453 {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
454 {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
455 {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
456 {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
457 {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
458 {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
459 {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
460 {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
461 {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
462 {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
463 {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
464 {}
465}
466;
467#else
468#error "Need to define SerDes protocol"
469#endif
470static const struct serdes_config *serdes_cfg_tbl[] = {
471 serdes1_cfg_tbl,
472 serdes2_cfg_tbl,
473 serdes3_cfg_tbl,
474 serdes4_cfg_tbl,
475};
476
477enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
478{
479 const struct serdes_config *ptr;
480
481 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
482 return 0;
483
484 ptr = serdes_cfg_tbl[serdes];
485 while (ptr->protocol) {
486 if (ptr->protocol == cfg)
487 return ptr->lanes[lane];
488 ptr++;
489 }
490 return 0;
491}
492
493int is_serdes_prtcl_valid(int serdes, u32 prtcl)
494{
495 int i;
496 const struct serdes_config *ptr;
497
498 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
499 return 0;
500
501 ptr = serdes_cfg_tbl[serdes];
502 while (ptr->protocol) {
503 if (ptr->protocol == prtcl)
504 break;
505 ptr++;
506 }
507
508 if (!ptr->protocol)
509 return 0;
510
511 for (i = 0; i < SRDS_MAX_LANES; i++) {
512 if (ptr->lanes[i] != NONE)
513 return 1;
514 }
515
516 return 0;
517}
518
