LXR uboot/board/freescale/t208xrdb/spl.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/* Copyright 2013 Freescale Semiconductor, Inc.
   3 */
   4
   5#include <common.h>
   6#include <clock_legacy.h>
   7#include <console.h>
   8#include <env_internal.h>
   9#include <init.h>
  10#include <malloc.h>
  11#include <ns16550.h>
  12#include <nand.h>
  13#include <i2c.h>
  14#include <mmc.h>
  15#include <fsl_esdhc.h>
  16#include <spi_flash.h>
  17#include "../common/spl.h"
  18
  19DECLARE_GLOBAL_DATA_PTR;
  20
  21phys_size_t get_effective_memsize(void)
  22{
  23        return CONFIG_SYS_L3_SIZE;
  24}
  25
  26unsigned long get_board_sys_clk(void)
  27{
  28        return CONFIG_SYS_CLK_FREQ;
  29}
  30
  31unsigned long get_board_ddr_clk(void)
  32{
  33        return CONFIG_DDR_CLK_FREQ;
  34}
  35
  36void board_init_f(ulong bootflag)
  37{
  38        u32 plat_ratio, sys_clk, ccb_clk;
  39        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  40
  41        /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
  42        memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
  43
  44        /* Update GD pointer */
  45        gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
  46
  47        console_init_f();
  48
  49        /* initialize selected port with appropriate baud rate */
  50        sys_clk = get_board_sys_clk();
  51        plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  52        ccb_clk = sys_clk * plat_ratio / 2;
  53
  54        NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  55                     ccb_clk / 16 / CONFIG_BAUDRATE);
  56
  57#if defined(CONFIG_SPL_MMC_BOOT)
  58        puts("\nSD boot...\n");
  59#elif defined(CONFIG_SPL_SPI_BOOT)
  60        puts("\nSPI boot...\n");
  61#elif defined(CONFIG_SPL_NAND_BOOT)
  62        puts("\nNAND boot...\n");
  63#endif
  64
  65        relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
  66}
  67
  68void board_init_r(gd_t *gd, ulong dest_addr)
  69{
  70        bd_t *bd;
  71
  72        bd = (bd_t *)(gd + sizeof(gd_t));
  73        memset(bd, 0, sizeof(bd_t));
  74        gd->bd = bd;
  75        bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
  76        bd->bi_memsize = CONFIG_SYS_L3_SIZE;
  77
  78        arch_cpu_init();
  79        get_clocks();
  80        mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  81                        CONFIG_SPL_RELOC_MALLOC_SIZE);
  82        gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  83
  84#ifdef CONFIG_SPL_NAND_BOOT
  85        nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  86                            (uchar *)SPL_ENV_ADDR);
  87#endif
  88#ifdef CONFIG_SPL_MMC_BOOT
  89        mmc_initialize(bd);
  90        mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  91                           (uchar *)SPL_ENV_ADDR);
  92#endif
  93#ifdef CONFIG_SPL_SPI_BOOT
  94        fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  95                               (uchar *)SPL_ENV_ADDR);
  96#endif
  97
  98        gd->env_addr  = (ulong)(SPL_ENV_ADDR);
  99        gd->env_valid = ENV_VALID;
 100
 101        i2c_init_all();
 102
 103        dram_init();
 104
 105#ifdef CONFIG_SPL_MMC_BOOT
 106        mmc_boot();
 107#elif defined(CONFIG_SPL_SPI_BOOT)
 108        fsl_spi_boot();
 109#elif defined(CONFIG_SPL_NAND_BOOT)
 110        nand_boot();
 111#endif
 112}
 113