LXR uboot/board/freescale/t4qds/spl.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/* Copyright 2014 Freescale Semiconductor, Inc.
   3 */
   4
   5#include <common.h>
   6#include <clock_legacy.h>
   7#include <console.h>
   8#include <env_internal.h>
   9#include <init.h>
  10#include <asm/spl.h>
  11#include <malloc.h>
  12#include <ns16550.h>
  13#include <nand.h>
  14#include <mmc.h>
  15#include <fsl_esdhc.h>
  16#include <i2c.h>
  17#include "../common/qixis.h"
  18#include "t4240qds_qixis.h"
  19
  20#define FSL_CORENET_CCSR_PORSR1_RCW_MASK        0xFF800000
  21
  22DECLARE_GLOBAL_DATA_PTR;
  23
  24phys_size_t get_effective_memsize(void)
  25{
  26        return CONFIG_SYS_L3_SIZE;
  27}
  28
  29unsigned long get_board_sys_clk(void)
  30{
  31        u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  32
  33        switch (sysclk_conf & 0x0F) {
  34        case QIXIS_SYSCLK_83:
  35                return 83333333;
  36        case QIXIS_SYSCLK_100:
  37                return 100000000;
  38        case QIXIS_SYSCLK_125:
  39                return 125000000;
  40        case QIXIS_SYSCLK_133:
  41                return 133333333;
  42        case QIXIS_SYSCLK_150:
  43                return 150000000;
  44        case QIXIS_SYSCLK_160:
  45                return 160000000;
  46        case QIXIS_SYSCLK_166:
  47                return 166666666;
  48        }
  49        return 66666666;
  50}
  51
  52unsigned long get_board_ddr_clk(void)
  53{
  54        u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  55
  56        switch ((ddrclk_conf & 0x30) >> 4) {
  57        case QIXIS_DDRCLK_100:
  58                return 100000000;
  59        case QIXIS_DDRCLK_125:
  60                return 125000000;
  61        case QIXIS_DDRCLK_133:
  62                return 133333333;
  63        }
  64        return 66666666;
  65}
  66
  67void board_init_f(ulong bootflag)
  68{
  69        u32 plat_ratio, sys_clk, ccb_clk;
  70        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  71#ifdef CONFIG_SPL_NAND_BOOT
  72        u32 porsr1, pinctl;
  73#endif
  74
  75#ifdef CONFIG_SPL_NAND_BOOT
  76        porsr1 = in_be32(&gur->porsr1);
  77        pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
  78        out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
  79#endif
  80        /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
  81        memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
  82
  83        /* Update GD pointer */
  84        gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
  85
  86        /* compiler optimization barrier needed for GCC >= 3.4 */
  87        __asm__ __volatile__("" : : : "memory");
  88
  89        console_init_f();
  90
  91        /* initialize selected port with appropriate baud rate */
  92        sys_clk = get_board_sys_clk();
  93        plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  94        ccb_clk = sys_clk * plat_ratio / 2;
  95
  96        NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  97                     ccb_clk / 16 / CONFIG_BAUDRATE);
  98
  99#ifdef CONFIG_SPL_MMC_BOOT
 100        puts("\nSD boot...\n");
 101#elif defined(CONFIG_SPL_NAND_BOOT)
 102        puts("\nNAND boot...\n");
 103#endif
 104        relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
 105}
 106
 107void board_init_r(gd_t *gd, ulong dest_addr)
 108{
 109        bd_t *bd;
 110
 111        bd = (bd_t *)(gd + sizeof(gd_t));
 112        memset(bd, 0, sizeof(bd_t));
 113        gd->bd = bd;
 114        bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
 115        bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 116
 117        arch_cpu_init();
 118        get_clocks();
 119        mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 120                        CONFIG_SPL_RELOC_MALLOC_SIZE);
 121        gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 122
 123#ifdef CONFIG_SPL_NAND_BOOT
 124        nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 125                            (uchar *)SPL_ENV_ADDR);
 126#endif
 127#ifdef CONFIG_SPL_MMC_BOOT
 128        mmc_initialize(bd);
 129        mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 130                           (uchar *)SPL_ENV_ADDR);
 131#endif
 132
 133        gd->env_addr  = (ulong)(SPL_ENV_ADDR);
 134        gd->env_valid = ENV_VALID;
 135
 136        i2c_init_all();
 137
 138        dram_init();
 139
 140#ifdef CONFIG_SPL_MMC_BOOT
 141        mmc_boot();
 142#elif defined(CONFIG_SPL_NAND_BOOT)
 143        nand_boot();
 144#endif
 145}
 146