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9#include <init.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/crm_regs.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/mach-imx/iomux-v3.h>
15#include <asm/mach-imx/mxc_i2c.h>
16#include <fsl_esdhc_imx.h>
17#include <linux/bitops.h>
18#include <miiphy.h>
19#include <netdev.h>
20#include <usb.h>
21#include <usb/ehci-ci.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
25int dram_init(void)
26{
27 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
28
29 return 0;
30}
31
32#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
33 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
34 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
35 PAD_CTL_HYS)
36
37static iomux_v3_cfg_t const uart1_pads[] = {
38 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
39 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
40};
41
42static iomux_v3_cfg_t const uart5_pads[] = {
43 MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
44 MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
45 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
46 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
47};
48
49static void setup_iomux_uart(void)
50{
51 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
52 imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
53}
54
55#ifdef CONFIG_NAND_MXS
56
57#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
58
59#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
60
61#define NANDREADYPC MUX_PAD_CTRL(NAND_PAD_READY0_CTRL)
62
63static iomux_v3_cfg_t const gpmi_pads[] = {
64 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
65 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
66 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
67 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
68 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
69 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
70 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
71 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
72 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
73 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
74 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
75 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
76 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
77 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | NANDREADYPC,
78};
79
80static void setup_gpmi_nand(void)
81{
82 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
83
84 setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
85 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
86}
87
88#endif
89
90#ifdef CONFIG_FEC_MXC
91
92#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
93
94#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
95 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
96 PAD_CTL_SRE_FAST)
97
98#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
99 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \
100 PAD_CTL_ODE)
101
102static iomux_v3_cfg_t const fec1_pads[] = {
103 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
104 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
105 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
106 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
107 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
108 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
109 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
110 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
111 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
112 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
113};
114
115static iomux_v3_cfg_t const fec2_pads[] = {
116 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
120 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
124};
125
126static void setup_iomux_fec(void)
127{
128 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
129 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
130}
131
132static int setup_fec(void)
133{
134 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
135 int ret;
136
137
138
139
140
141 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
142 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
143
144 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
145 if (ret)
146 return ret;
147
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150
151
152 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
153 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
154
155 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
156 if (ret)
157 return ret;
158
159 enable_enet_clk(1);
160
161 return 0;
162}
163
164int board_phy_config(struct phy_device *phydev)
165{
166
167
168
169
170 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
171
172 if (phydev->drv->config)
173 phydev->drv->config(phydev);
174
175 return 0;
176}
177#endif
178
179int board_early_init_f(void)
180{
181 setup_iomux_uart();
182#ifdef CONFIG_FEC_MXC
183 setup_iomux_fec();
184#endif
185
186 return 0;
187}
188
189int board_init(void)
190{
191
192 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
193
194#ifdef CONFIG_NAND_MXS
195 setup_gpmi_nand();
196#endif
197
198#ifdef CONFIG_FEC_MXC
199 setup_fec();
200#endif
201 return 0;
202}
203
204int checkboard(void)
205{
206 u32 cpurev = get_cpu_rev();
207
208 printf("Board: PHYTEC phyCORE-i.MX%s\n",
209 get_imx_type((cpurev & 0xFF000) >> 12));
210
211 return 0;
212}
213
