LXR uboot/board/renesas/silk/silk.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * board/renesas/silk/silk.c
   4 *
   5 * Copyright (C) 2015 Renesas Electronics Corporation
   6 * Copyright (C) 2015 Cogent Embedded, Inc.
   7 */
   8
   9#include <common.h>
  10#include <cpu_func.h>
  11#include <env.h>
  12#include <hang.h>
  13#include <malloc.h>
  14#include <dm.h>
  15#include <dm/platform_data/serial_sh.h>
  16#include <env_internal.h>
  17#include <asm/processor.h>
  18#include <asm/mach-types.h>
  19#include <asm/io.h>
  20#include <linux/errno.h>
  21#include <asm/arch/sys_proto.h>
  22#include <asm/gpio.h>
  23#include <asm/arch/rmobile.h>
  24#include <asm/arch/rcar-mstp.h>
  25#include <asm/arch/mmc.h>
  26#include <asm/arch/sh_sdhi.h>
  27#include <netdev.h>
  28#include <miiphy.h>
  29#include <i2c.h>
  30#include <div64.h>
  31#include "qos.h"
  32
  33DECLARE_GLOBAL_DATA_PTR;
  34
  35void s_init(void)
  36{
  37        struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  38        struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  39
  40        /* Watchdog init */
  41        writel(0xA5A5A500, &rwdt->rwtcsra);
  42        writel(0xA5A5A500, &swdt->swtcsra);
  43
  44        /* QoS */
  45        qos_init();
  46}
  47
  48#define TMU0_MSTP125    BIT(25)
  49#define MMC0_MSTP315    BIT(15)
  50
  51#define SD1CKCR         0xE6150078
  52#define SD_97500KHZ     0x7
  53
  54int board_early_init_f(void)
  55{
  56        /* TMU */
  57        mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  58
  59        /* Set SD1 to the 97.5MHz */
  60        writel(SD_97500KHZ, SD1CKCR);
  61
  62        return 0;
  63}
  64
  65#define ETHERNET_PHY_RESET      56      /* GPIO 1 24 */
  66
  67int board_init(void)
  68{
  69        /* adress of boot parameters */
  70        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  71
  72        /* Force ethernet PHY out of reset */
  73        gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  74        gpio_direction_output(ETHERNET_PHY_RESET, 0);
  75        mdelay(20);
  76        gpio_direction_output(ETHERNET_PHY_RESET, 1);
  77        udelay(1);
  78
  79        return 0;
  80}
  81
  82int dram_init(void)
  83{
  84        if (fdtdec_setup_mem_size_base() != 0)
  85                return -EINVAL;
  86
  87        return 0;
  88}
  89
  90int dram_init_banksize(void)
  91{
  92        fdtdec_setup_memory_banksize();
  93
  94        return 0;
  95}
  96
  97/* porter has KSZ8041RNLI */
  98#define PHY_CONTROL1            0x1E
  99#define PHY_LED_MODE            0xC000
 100#define PHY_LED_MODE_ACK        0x4000
 101int board_phy_config(struct phy_device *phydev)
 102{
 103        int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
 104        ret &= ~PHY_LED_MODE;
 105        ret |= PHY_LED_MODE_ACK;
 106        ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
 107
 108        return 0;
 109}
 110
 111void reset_cpu(ulong addr)
 112{
 113        struct udevice *dev;
 114        const u8 pmic_bus = 1;
 115        const u8 pmic_addr = 0x5a;
 116        u8 data;
 117        int ret;
 118
 119        ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
 120        if (ret)
 121                hang();
 122
 123        ret = dm_i2c_read(dev, 0x13, &data, 1);
 124        if (ret)
 125                hang();
 126
 127        data |= BIT(1);
 128
 129        ret = dm_i2c_write(dev, 0x13, &data, 1);
 130        if (ret)
 131                hang();
 132}
 133
 134enum env_location env_get_location(enum env_operation op, int prio)
 135{
 136        const u32 load_magic = 0xb33fc0de;
 137
 138        /* Block environment access if loaded using JTAG */
 139        if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
 140            (op != ENVOP_INIT))
 141                return ENVL_UNKNOWN;
 142
 143        if (prio)
 144                return ENVL_UNKNOWN;
 145
 146        return ENVL_SPI_FLASH;
 147}
 148