uboot/drivers/i2c/fsl_i2c.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright 2006,2009 Freescale Semiconductor, Inc.
   4 *
   5 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6 * Changes for multibus/multiadapter I2C support.
   7 */
   8
   9#include <common.h>
  10#include <command.h>
  11#include <i2c.h>                /* Functional interface */
  12#include <time.h>
  13#include <asm/io.h>
  14#include <asm/fsl_i2c.h>        /* HW definitions */
  15#include <clk.h>
  16#include <dm.h>
  17#include <mapmem.h>
  18
  19/* The maximum number of microseconds we will wait until another master has
  20 * released the bus.  If not defined in the board header file, then use a
  21 * generic value.
  22 */
  23#ifndef CONFIG_I2C_MBB_TIMEOUT
  24#define CONFIG_I2C_MBB_TIMEOUT  100000
  25#endif
  26
  27/* The maximum number of microseconds we will wait for a read or write
  28 * operation to complete.  If not defined in the board header file, then use a
  29 * generic value.
  30 */
  31#ifndef CONFIG_I2C_TIMEOUT
  32#define CONFIG_I2C_TIMEOUT      100000
  33#endif
  34
  35#define I2C_READ_BIT  1
  36#define I2C_WRITE_BIT 0
  37
  38DECLARE_GLOBAL_DATA_PTR;
  39
  40#ifndef CONFIG_DM_I2C
  41static const struct fsl_i2c_base *i2c_base[4] = {
  42        (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
  43#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
  44        (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
  45#endif
  46#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
  47        (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
  48#endif
  49#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
  50        (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
  51#endif
  52};
  53#endif
  54
  55/* I2C speed map for a DFSR value of 1 */
  56
  57#ifdef __M68K__
  58/*
  59 * Map I2C frequency dividers to FDR and DFSR values
  60 *
  61 * This structure is used to define the elements of a table that maps I2C
  62 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
  63 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
  64 * Sampling Rate (DFSR) registers.
  65 *
  66 * The actual table should be defined in the board file, and it must be called
  67 * fsl_i2c_speed_map[].
  68 *
  69 * The last entry of the table must have a value of {-1, X}, where X is same
  70 * FDR/DFSR values as the second-to-last entry.  This guarantees that any
  71 * search through the array will always find a match.
  72 *
  73 * The values of the divider must be in increasing numerical order, i.e.
  74 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
  75 *
  76 * For this table, the values are based on a value of 1 for the DFSR
  77 * register.  See the application note AN2919 "Determining the I2C Frequency
  78 * Divider Ratio for SCL"
  79 *
  80 * ColdFire I2C frequency dividers for FDR values are different from
  81 * PowerPC. The protocol to use the I2C module is still the same.
  82 * A different table is defined and are based on MCF5xxx user manual.
  83 *
  84 */
  85static const struct {
  86        unsigned short divider;
  87        u8 fdr;
  88} fsl_i2c_speed_map[] = {
  89        {20, 32}, {22, 33}, {24, 34}, {26, 35},
  90        {28, 0}, {28, 36}, {30, 1}, {32, 37},
  91        {34, 2}, {36, 38}, {40, 3}, {40, 39},
  92        {44, 4}, {48, 5}, {48, 40}, {56, 6},
  93        {56, 41}, {64, 42}, {68, 7}, {72, 43},
  94        {80, 8}, {80, 44}, {88, 9}, {96, 41},
  95        {104, 10}, {112, 42}, {128, 11}, {128, 43},
  96        {144, 12}, {160, 13}, {160, 48}, {192, 14},
  97        {192, 49}, {224, 50}, {240, 15}, {256, 51},
  98        {288, 16}, {320, 17}, {320, 52}, {384, 18},
  99        {384, 53}, {448, 54}, {480, 19}, {512, 55},
 100        {576, 20}, {640, 21}, {640, 56}, {768, 22},
 101        {768, 57}, {960, 23}, {896, 58}, {1024, 59},
 102        {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
 103        {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
 104        {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
 105        {-1, 31}
 106};
 107#endif
 108
 109/**
 110 * Set the I2C bus speed for a given I2C device
 111 *
 112 * @param base: the I2C device registers
 113 * @i2c_clk: I2C bus clock frequency
 114 * @speed: the desired speed of the bus
 115 *
 116 * The I2C device must be stopped before calling this function.
 117 *
 118 * The return value is the actual bus speed that is set.
 119 */
 120static uint set_i2c_bus_speed(const struct fsl_i2c_base *base,
 121                              uint i2c_clk, uint speed)
 122{
 123        ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX);
 124
 125        /*
 126         * We want to choose an FDR/DFSR that generates an I2C bus speed that
 127         * is equal to or lower than the requested speed.  That means that we
 128         * want the first divider that is equal to or greater than the
 129         * calculated divider.
 130         */
 131#ifdef __PPC__
 132        u8 dfsr, fdr = 0x31; /* Default if no FDR found */
 133        /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
 134        ushort a, b, ga, gb;
 135        ulong c_div, est_div;
 136
 137#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
 138        dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
 139#else
 140        /* Condition 1: dfsr <= 50/T */
 141        dfsr = (5 * (i2c_clk / 1000)) / 100000;
 142#endif
 143#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
 144        fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
 145        speed = i2c_clk / divider; /* Fake something */
 146#else
 147        debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
 148        if (!dfsr)
 149                dfsr = 1;
 150
 151        est_div = ~0;
 152        for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
 153                for (gb = 0; gb < 8; gb++) {
 154                        b = 16 << gb;
 155                        c_div = b * (a + ((3 * dfsr) / b) * 2);
 156                        if (c_div > divider && c_div < est_div) {
 157                                ushort bin_gb, bin_ga;
 158
 159                                est_div = c_div;
 160                                bin_gb = gb << 2;
 161                                bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
 162                                fdr = bin_gb | bin_ga;
 163                                speed = i2c_clk / est_div;
 164
 165                                debug("FDR: 0x%.2x, ", fdr);
 166                                debug("div: %ld, ", est_div);
 167                                debug("ga: 0x%x, gb: 0x%x, ", ga, gb);
 168                                debug("a: %d, b: %d, speed: %d\n", a, b, speed);
 169
 170                                /* Condition 2 not accounted for */
 171                                debug("Tr <= %d ns\n",
 172                                      (b - 3 * dfsr) * 1000000 /
 173                                      (i2c_clk / 1000));
 174                        }
 175                }
 176                if (a == 20)
 177                        a += 2;
 178                if (a == 24)
 179                        a += 4;
 180        }
 181        debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr);
 182        debug("FDR: 0x%.2x, speed: %d\n", fdr, speed);
 183#endif
 184        writeb(dfsr, &base->dfsrr);     /* set default filter */
 185        writeb(fdr, &base->fdr);        /* set bus speed */
 186#else
 187        uint i;
 188
 189        for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
 190                if (fsl_i2c_speed_map[i].divider >= divider) {
 191                        u8 fdr;
 192
 193                        fdr = fsl_i2c_speed_map[i].fdr;
 194                        speed = i2c_clk / fsl_i2c_speed_map[i].divider;
 195                        writeb(fdr, &base->fdr);        /* set bus speed */
 196
 197                        break;
 198                }
 199#endif
 200        return speed;
 201}
 202
 203#ifndef CONFIG_DM_I2C
 204static uint get_i2c_clock(int bus)
 205{
 206        if (bus)
 207                return gd->arch.i2c2_clk;       /* I2C2 clock */
 208        else
 209                return gd->arch.i2c1_clk;       /* I2C1 clock */
 210}
 211#endif
 212
 213static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
 214{
 215        const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 216        unsigned long long timeval = 0;
 217        int ret = -1;
 218        uint flags = 0;
 219
 220#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 221        uint svr = get_svr();
 222
 223        if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
 224            (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
 225                flags = I2C_CR_BIT6;
 226#endif
 227
 228        writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
 229
 230        timeval = get_ticks();
 231        while (!(readb(&base->sr) & I2C_SR_MBB)) {
 232                if ((get_ticks() - timeval) > timeout)
 233                        goto err;
 234        }
 235
 236        if (readb(&base->sr) & I2C_SR_MAL) {
 237                /* SDA is stuck low */
 238                writeb(0, &base->cr);
 239                udelay(100);
 240                writeb(I2C_CR_MSTA | flags, &base->cr);
 241                writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
 242        }
 243
 244        readb(&base->dr);
 245
 246        timeval = get_ticks();
 247        while (!(readb(&base->sr) & I2C_SR_MIF)) {
 248                if ((get_ticks() - timeval) > timeout)
 249                        goto err;
 250        }
 251        ret = 0;
 252
 253err:
 254        writeb(I2C_CR_MEN | flags, &base->cr);
 255        writeb(0, &base->sr);
 256        udelay(100);
 257
 258        return ret;
 259}
 260
 261static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
 262                       slaveadd, int i2c_clk, int busnum)
 263{
 264        const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 265        unsigned long long timeval;
 266
 267#ifdef CONFIG_SYS_I2C_INIT_BOARD
 268        /* Call board specific i2c bus reset routine before accessing the
 269         * environment, which might be in a chip on that bus. For details
 270         * about this problem see doc/I2C_Edge_Conditions.
 271         */
 272        i2c_init_board();
 273#endif
 274        writeb(0, &base->cr);           /* stop I2C controller */
 275        udelay(5);                      /* let it shutdown in peace */
 276        set_i2c_bus_speed(base, i2c_clk, speed);
 277        writeb(slaveadd << 1, &base->adr);/* write slave address */
 278        writeb(0x0, &base->sr);         /* clear status register */
 279        writeb(I2C_CR_MEN, &base->cr);  /* start I2C controller */
 280
 281        timeval = get_ticks();
 282        while (readb(&base->sr) & I2C_SR_MBB) {
 283                if ((get_ticks() - timeval) < timeout)
 284                        continue;
 285
 286                if (fsl_i2c_fixup(base))
 287                        debug("i2c_init: BUS#%d failed to init\n",
 288                              busnum);
 289
 290                break;
 291        }
 292}
 293
 294static int i2c_wait4bus(const struct fsl_i2c_base *base)
 295{
 296        unsigned long long timeval = get_ticks();
 297        const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 298
 299        while (readb(&base->sr) & I2C_SR_MBB) {
 300                if ((get_ticks() - timeval) > timeout)
 301                        return -1;
 302        }
 303
 304        return 0;
 305}
 306
 307static int i2c_wait(const struct fsl_i2c_base *base, int write)
 308{
 309        u32 csr;
 310        unsigned long long timeval = get_ticks();
 311        const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
 312
 313        do {
 314                csr = readb(&base->sr);
 315                if (!(csr & I2C_SR_MIF))
 316                        continue;
 317                /* Read again to allow register to stabilise */
 318                csr = readb(&base->sr);
 319
 320                writeb(0x0, &base->sr);
 321
 322                if (csr & I2C_SR_MAL) {
 323                        debug("%s: MAL\n", __func__);
 324                        return -1;
 325                }
 326
 327                if (!(csr & I2C_SR_MCF))        {
 328                        debug("%s: unfinished\n", __func__);
 329                        return -1;
 330                }
 331
 332                if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
 333                        debug("%s: No RXACK\n", __func__);
 334                        return -1;
 335                }
 336
 337                return 0;
 338        } while ((get_ticks() - timeval) < timeout);
 339
 340        debug("%s: timed out\n", __func__);
 341        return -1;
 342}
 343
 344static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
 345                          u8 dir, int rsta)
 346{
 347        writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
 348               | (rsta ? I2C_CR_RSTA : 0),
 349               &base->cr);
 350
 351        writeb((dev << 1) | dir, &base->dr);
 352
 353        if (i2c_wait(base, I2C_WRITE_BIT) < 0)
 354                return 0;
 355
 356        return 1;
 357}
 358
 359static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data,
 360                            int length)
 361{
 362        int i;
 363
 364        for (i = 0; i < length; i++) {
 365                writeb(data[i], &base->dr);
 366
 367                if (i2c_wait(base, I2C_WRITE_BIT) < 0)
 368                        break;
 369        }
 370
 371        return i;
 372}
 373
 374static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
 375                           int length)
 376{
 377        int i;
 378
 379        writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
 380               &base->cr);
 381
 382        /* dummy read */
 383        readb(&base->dr);
 384
 385        for (i = 0; i < length; i++) {
 386                if (i2c_wait(base, I2C_READ_BIT) < 0)
 387                        break;
 388
 389                /* Generate ack on last next to last byte */
 390                if (i == length - 2)
 391                        writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
 392                               &base->cr);
 393
 394                /* Do not generate stop on last byte */
 395                if (i == length - 1)
 396                        writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
 397                               &base->cr);
 398
 399                data[i] = readb(&base->dr);
 400        }
 401
 402        return i;
 403}
 404
 405static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset,
 406                      int olen, u8 *data, int dlen)
 407{
 408        int ret = -1; /* signal error */
 409
 410        if (i2c_wait4bus(base) < 0)
 411                return -1;
 412
 413        /* Some drivers use offset lengths in excess of 4 bytes. These drivers
 414         * adhere to the following convention:
 415         * - the offset length is passed as negative (that is, the absolute
 416         *   value of olen is the actual offset length)
 417         * - the offset itself is passed in data, which is overwritten by the
 418         *   subsequent read operation
 419         */
 420        if (olen < 0) {
 421                if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
 422                        ret = __i2c_write_data(base, data, -olen);
 423
 424                if (ret != -olen)
 425                        return -1;
 426
 427                if (dlen && i2c_write_addr(base, chip_addr,
 428                                           I2C_READ_BIT, 1) != 0)
 429                        ret = __i2c_read_data(base, data, dlen);
 430        } else {
 431                if ((!dlen || olen > 0) &&
 432                    i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0  &&
 433                    __i2c_write_data(base, offset, olen) == olen)
 434                        ret = 0; /* No error so far */
 435
 436                if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
 437                                           olen ? 1 : 0) != 0)
 438                        ret = __i2c_read_data(base, data, dlen);
 439        }
 440
 441        writeb(I2C_CR_MEN, &base->cr);
 442
 443        if (i2c_wait4bus(base)) /* Wait until STOP */
 444                debug("i2c_read: wait4bus timed out\n");
 445
 446        if (ret == dlen)
 447                return 0;
 448
 449        return -1;
 450}
 451
 452static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr,
 453                       u8 *offset, int olen, u8 *data, int dlen)
 454{
 455        int ret = -1; /* signal error */
 456
 457        if (i2c_wait4bus(base) < 0)
 458                return -1;
 459
 460        if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
 461            __i2c_write_data(base, offset, olen) == olen) {
 462                ret = __i2c_write_data(base, data, dlen);
 463        }
 464
 465        writeb(I2C_CR_MEN, &base->cr);
 466        if (i2c_wait4bus(base)) /* Wait until STOP */
 467                debug("i2c_write: wait4bus timed out\n");
 468
 469        if (ret == dlen)
 470                return 0;
 471
 472        return -1;
 473}
 474
 475static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
 476{
 477        /* For unknown reason the controller will ACK when
 478         * probing for a slave with the same address, so skip
 479         * it.
 480         */
 481        if (chip == (readb(&base->adr) >> 1))
 482                return -1;
 483
 484        return __i2c_read(base, chip, 0, 0, NULL, 0);
 485}
 486
 487static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base,
 488                                uint speed, int i2c_clk)
 489{
 490        writeb(0, &base->cr);           /* stop controller */
 491        set_i2c_bus_speed(base, i2c_clk, speed);
 492        writeb(I2C_CR_MEN, &base->cr);  /* start controller */
 493
 494        return 0;
 495}
 496
 497#ifndef CONFIG_DM_I2C
 498static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 499{
 500        __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
 501                   get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
 502}
 503
 504static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
 505{
 506        return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
 507}
 508
 509static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset,
 510                        int olen, u8 *data, int dlen)
 511{
 512        u8 *o = (u8 *)&offset;
 513
 514        return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
 515                          olen, data, dlen);
 516}
 517
 518static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset,
 519                         int olen, u8 *data, int dlen)
 520{
 521        u8 *o = (u8 *)&offset;
 522
 523        return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
 524                           olen, data, dlen);
 525}
 526
 527static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 528{
 529        return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
 530                                   get_i2c_clock(adap->hwadapnr));
 531}
 532
 533/*
 534 * Register fsl i2c adapters
 535 */
 536U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 537                         fsl_i2c_write, fsl_i2c_set_bus_speed,
 538                         CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
 539                         0)
 540#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
 541U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 542                         fsl_i2c_write, fsl_i2c_set_bus_speed,
 543                         CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
 544                         1)
 545#endif
 546#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
 547U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 548                         fsl_i2c_write, fsl_i2c_set_bus_speed,
 549                         CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
 550                         2)
 551#endif
 552#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
 553U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 554                         fsl_i2c_write, fsl_i2c_set_bus_speed,
 555                         CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
 556                         3)
 557#endif
 558#else /* CONFIG_DM_I2C */
 559static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
 560                              u32 chip_flags)
 561{
 562        struct fsl_i2c_dev *dev = dev_get_priv(bus);
 563
 564        return __i2c_probe_chip(dev->base, chip_addr);
 565}
 566
 567static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed)
 568{
 569        struct fsl_i2c_dev *dev = dev_get_priv(bus);
 570
 571        return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
 572}
 573
 574static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
 575{
 576        struct fsl_i2c_dev *dev = dev_get_priv(bus);
 577        struct clk clock;
 578
 579        dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base));
 580
 581        if (!dev->base)
 582                return -ENOMEM;
 583
 584        dev->index = dev_read_u32_default(bus, "cell-index", -1);
 585        dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr",
 586                                             0x7f);
 587        dev->speed = dev_read_u32_default(bus, "clock-frequency",
 588                                          I2C_SPEED_FAST_RATE);
 589
 590        if (!clk_get_by_index(bus, 0, &clock))
 591                dev->i2c_clk = clk_get_rate(&clock);
 592        else
 593                dev->i2c_clk = dev->index ? gd->arch.i2c2_clk :
 594                                            gd->arch.i2c1_clk;
 595
 596        return 0;
 597}
 598
 599static int fsl_i2c_probe(struct udevice *bus)
 600{
 601        struct fsl_i2c_dev *dev = dev_get_priv(bus);
 602
 603        __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
 604                   dev->index);
 605        return 0;
 606}
 607
 608static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 609{
 610        struct fsl_i2c_dev *dev = dev_get_priv(bus);
 611        struct i2c_msg *dmsg, *omsg, dummy;
 612
 613        memset(&dummy, 0, sizeof(struct i2c_msg));
 614
 615        /* We expect either two messages (one with an offset and one with the
 616         * actual data) or one message (just data)
 617         */
 618        if (nmsgs > 2 || nmsgs == 0) {
 619                debug("%s: Only one or two messages are supported.", __func__);
 620                return -1;
 621        }
 622
 623        omsg = nmsgs == 1 ? &dummy : msg;
 624        dmsg = nmsgs == 1 ? msg : msg + 1;
 625
 626        if (dmsg->flags & I2C_M_RD)
 627                return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
 628                                  dmsg->buf, dmsg->len);
 629        else
 630                return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
 631                                   dmsg->buf, dmsg->len);
 632}
 633
 634static const struct dm_i2c_ops fsl_i2c_ops = {
 635        .xfer           = fsl_i2c_xfer,
 636        .probe_chip     = fsl_i2c_probe_chip,
 637        .set_bus_speed  = fsl_i2c_set_bus_speed,
 638};
 639
 640static const struct udevice_id fsl_i2c_ids[] = {
 641        { .compatible = "fsl-i2c", },
 642        { /* sentinel */ }
 643};
 644
 645U_BOOT_DRIVER(i2c_fsl) = {
 646        .name = "i2c_fsl",
 647        .id = UCLASS_I2C,
 648        .of_match = fsl_i2c_ids,
 649        .probe = fsl_i2c_probe,
 650        .ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
 651        .priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
 652        .ops = &fsl_i2c_ops,
 653};
 654
 655#endif /* CONFIG_DM_I2C */
 656