1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Freescale MCF5208EVBe. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9#ifndef _M5208EVBE_H 10#define _M5208EVBE_H 11 12/* 13 * High Level Configuration Options 14 * (easy to change) 15 */ 16#define CONFIG_MCFUART 17#define CONFIG_SYS_UART_PORT (0) 18 19#undef CONFIG_WATCHDOG 20#define CONFIG_WATCHDOG_TIMEOUT 5000 21 22#ifdef CONFIG_MCFFEC 23# define CONFIG_MII_INIT 1 24# define CONFIG_SYS_DISCOVER_PHY 25# define CONFIG_SYS_RX_ETH_BUFFER 8 26# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 27# define CONFIG_HAS_ETH1 28/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 29# ifndef CONFIG_SYS_DISCOVER_PHY 30# define FECDUPLEX FULL 31# define FECSPEED _100BASET 32# else 33# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 34# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 35# endif 36# endif /* CONFIG_SYS_DISCOVER_PHY */ 37#endif 38 39/* Timer */ 40#define CONFIG_MCFTMR 41 42/* I2C */ 43#define CONFIG_SYS_I2C 44#define CONFIG_SYS_I2C_FSL 45#define CONFIG_SYS_FSL_I2C_SPEED 80000 46#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 47#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 48#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 49 50#define CONFIG_UDP_CHECKSUM 51 52#ifdef CONFIG_MCFFEC 53# define CONFIG_IPADDR 192.162.1.2 54# define CONFIG_NETMASK 255.255.255.0 55# define CONFIG_SERVERIP 192.162.1.1 56# define CONFIG_GATEWAYIP 192.162.1.1 57#endif /* CONFIG_MCFFEC */ 58 59#define CONFIG_HOSTNAME "M5208EVBe" 60#define CONFIG_EXTRA_ENV_SETTINGS \ 61 "netdev=eth0\0" \ 62 "loadaddr=40010000\0" \ 63 "u-boot=u-boot.bin\0" \ 64 "load=tftp ${loadaddr) ${u-boot}\0" \ 65 "upd=run load; run prog\0" \ 66 "prog=prot off 0 3ffff;" \ 67 "era 0 3ffff;" \ 68 "cp.b ${loadaddr} 0 ${filesize};" \ 69 "save\0" \ 70 "" 71 72#define CONFIG_PRAM 512 /* 512 KB */ 73 74#define CONFIG_SYS_LOAD_ADDR 0x40010000 75 76#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ 77#define CONFIG_SYS_PLL_ODR 0x36 78#define CONFIG_SYS_PLL_FDR 0x7D 79 80#define CONFIG_SYS_MBAR 0xFC000000 81 82/* 83 * Low Level Configuration Settings 84 * (address mappings, register initial values, etc.) 85 * You should know what you are doing if you make changes here. 86 */ 87/* Definitions for initial stack pointer and data area (in DPRAM) */ 88#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 89#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ 90#define CONFIG_SYS_INIT_RAM_CTRL 0x221 91#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 92#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 93 94/* 95 * Start addresses for the final memory configuration 96 * (Set up by the startup code) 97 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 98 */ 99#define CONFIG_SYS_SDRAM_BASE 0x40000000 100#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 101#define CONFIG_SYS_SDRAM_CFG1 0x43711630 102#define CONFIG_SYS_SDRAM_CFG2 0x56670000 103#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 104#define CONFIG_SYS_SDRAM_EMOD 0x80010000 105#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 106 107#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 108#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 109 110#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 111#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 112 113#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 114#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 115 116/* 117 * For booting Linux, the board info and command line data 118 * have to be in the first 8 MB of memory, since this is 119 * the maximum mapped by the Linux kernel during initialization ?? 120 */ 121#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 122#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 123 124/* FLASH organization */ 125#ifdef CONFIG_SYS_FLASH_CFI 126# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 127# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 128# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 129# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ 130#endif 131 132#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 133 134/* 135 * Configuration for environment 136 * Environment is embedded in u-boot in the second sector of the flash 137 */ 138 139#define LDS_BOARD_TEXT \ 140 . = DEFINED(env_offset) ? env_offset : .; \ 141 env/embedded.o(.text*); 142 143/* Cache Configuration */ 144#define CONFIG_SYS_CACHELINE_SIZE 16 145 146#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 147 CONFIG_SYS_INIT_RAM_SIZE - 8) 148#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 149 CONFIG_SYS_INIT_RAM_SIZE - 4) 150#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 151#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 152 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 153 CF_ACR_EN | CF_ACR_SM_ALL) 154#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 155 CF_CACR_DISD | CF_CACR_INVI | \ 156 CF_CACR_CEIB | CF_CACR_DCM | \ 157 CF_CACR_EUSP) 158 159/* Chipselect bank definitions */ 160/* 161 * CS0 - NOR Flash 162 * CS1 - Available 163 * CS2 - Available 164 * CS3 - Available 165 * CS4 - Available 166 * CS5 - Available 167 */ 168#define CONFIG_SYS_CS0_BASE 0 169#define CONFIG_SYS_CS0_MASK 0x007F0001 170#define CONFIG_SYS_CS0_CTRL 0x00001FA0 171 172#endif /* _M5208EVBE_H */ 173