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8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12
13
14
15#define CONFIG_E300 1
16
17#ifndef CONFIG_SYS_MONITOR_BASE
18#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
19#endif
20
21#define CONFIG_PCI_INDIRECT_BRIDGE
22
23
24
25
26
27
28
29#define CONFIG_VSC7385_ENET
30#define CONFIG_TSEC2
31
32#define CONFIG_SYS_MEMTEST_START 0x00001000
33#define CONFIG_SYS_MEMTEST_END 0x07f00000
34
35
36
37
38
39#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
40
41
42
43
44
45
46
47#ifdef CONFIG_VSC7385_ENET
48
49#define CONFIG_TSEC1
50
51
52#define CONFIG_VSC7385_IMAGE 0xFE7FE000
53#define CONFIG_VSC7385_IMAGE_SIZE 8192
54
55#endif
56
57
58
59
60#define CONFIG_SYS_SDRAM_BASE 0x00000000
61
62
63
64
65
66#define CONFIG_SYS_DDR_SIZE 128
67#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
68 | CSCONFIG_ODT_RD_NEVER \
69 | CSCONFIG_ODT_WR_ONLY_CURRENT \
70 | CSCONFIG_ROW_BIT_13 \
71 | CSCONFIG_COL_BIT_10)
72
73
74#define CONFIG_SYS_DDR_TIMING_3 0x00000000
75#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
76 | (0 << TIMING_CFG0_WRT_SHIFT) \
77 | (0 << TIMING_CFG0_RRT_SHIFT) \
78 | (0 << TIMING_CFG0_WWT_SHIFT) \
79 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
80 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
81 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
82 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
83
84#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
85 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
86 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
87 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
88 | (10 << TIMING_CFG1_REFREC_SHIFT) \
89 | (3 << TIMING_CFG1_WRREC_SHIFT) \
90 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
91 | (2 << TIMING_CFG1_WRTORD_SHIFT))
92
93#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
94 | (5 << TIMING_CFG2_CPO_SHIFT) \
95 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
96 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
97 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
98 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
99 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
100
101#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
102 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
103
104#if defined(CONFIG_DDR_2T_TIMING)
105#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
106 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
107 | SDRAM_CFG_DBW_32 \
108 | SDRAM_CFG_2T_EN)
109
110#else
111#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
112 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
113 | SDRAM_CFG_DBW_32)
114
115#endif
116#define CONFIG_SYS_SDRAM_CFG2 0x00401000
117
118#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
119 | (0x0632 << SDRAM_MODE_SD_SHIFT))
120
121#define CONFIG_SYS_DDR_MODE_2 0x8000C000
122
123#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
124
125#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
126 | DDRCDR_PZ_NOMZ \
127 | DDRCDR_NZ_NOMZ \
128 | DDRCDR_M_ODR)
129
130
131
132
133#define CONFIG_SYS_FLASH_BASE 0xFE000000
134#define CONFIG_SYS_FLASH_SIZE 8
135#define CONFIG_SYS_FLASH_PROTECTION 1
136#define CONFIG_SYS_FLASH_EMPTY_INFO
137
138#define CONFIG_SYS_MAX_FLASH_BANKS 1
139#define CONFIG_SYS_MAX_FLASH_SECT 135
140
141#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
142#define CONFIG_SYS_FLASH_WRITE_TOUT 500
143
144#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
145 !defined(CONFIG_SPL_BUILD)
146#define CONFIG_SYS_RAMBOOT
147#endif
148
149#define CONFIG_SYS_INIT_RAM_LOCK 1
150#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
151#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
152
153#define CONFIG_SYS_GBL_DATA_OFFSET \
154 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
155#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
156
157
158#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
159#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
160
161
162#define CONFIG_SYS_NAND_BASE 0xE2800000
163
164#define CONFIG_MTD_PARTITION
165
166#define CONFIG_SYS_MAX_NAND_DEVICE 1
167#define CONFIG_NAND_FSL_ELBC 1
168#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
169#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
170
171
172#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
173#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
174
175
176#define CONFIG_SYS_BCSR_ADDR 0xFA000000
177#define CONFIG_SYS_BCSR_SIZE (32 * 1024)
178
179
180
181#ifdef CONFIG_VSC7385_ENET
182
183
184#define CONFIG_SYS_VSC7385_BASE 0xF0000000
185#define CONFIG_SYS_VSC7385_SIZE (128 * 1024)
186
187
188#endif
189
190#define CONFIG_MPC83XX_GPIO 1
191
192
193
194
195#define CONFIG_SYS_NS16550_SERIAL
196#define CONFIG_SYS_NS16550_REG_SIZE 1
197
198#define CONFIG_SYS_BAUDRATE_TABLE \
199 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
200
201#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
202#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
203
204
205#define CONFIG_SYS_I2C
206#define CONFIG_SYS_I2C_FSL
207#define CONFIG_SYS_FSL_I2C_SPEED 400000
208#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
209#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
210#define CONFIG_SYS_FSL_I2C2_SPEED 400000
211#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
212#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
213#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
214
215
216
217
218
219#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
220#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
221#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
222#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
223#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
224#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
225#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
226#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
227#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
228
229#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
230
231
232
233
234
235#define CONFIG_GMII
236
237#ifdef CONFIG_TSEC1
238#define CONFIG_HAS_ETH0
239#define CONFIG_TSEC1_NAME "TSEC0"
240#define CONFIG_SYS_TSEC1_OFFSET 0x24000
241#define TSEC1_PHY_ADDR 0x1c
242#define TSEC1_FLAGS TSEC_GIGABIT
243#define TSEC1_PHYIDX 0
244#endif
245
246#ifdef CONFIG_TSEC2
247#define CONFIG_HAS_ETH1
248#define CONFIG_TSEC2_NAME "TSEC1"
249#define CONFIG_SYS_TSEC2_OFFSET 0x25000
250#define TSEC2_PHY_ADDR 4
251#define TSEC2_FLAGS TSEC_GIGABIT
252#define TSEC2_PHYIDX 0
253#endif
254
255
256#define CONFIG_ETHPRIME "TSEC1"
257
258
259
260
261#define CONFIG_RTC_DS1337
262#define CONFIG_SYS_I2C_RTC_ADDR 0x68
263
264
265
266
267#if !defined(CONFIG_SYS_RAMBOOT)
268
269#endif
270
271#define CONFIG_LOADS_ECHO 1
272#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
273
274
275
276
277#define CONFIG_BOOTP_BOOTFILESIZE
278
279
280
281
282
283
284
285
286#define CONFIG_SYS_LOAD_ADDR 0x2000000
287#define CONFIG_SYS_CBSIZE 1024
288
289
290#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
291
292
293
294
295
296
297
298#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
299#define CONFIG_SYS_BOOTM_LEN (64 << 20)
300
301#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
302
303#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
304
305
306#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2)
307
308#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
309
310
311
312
313#define CONFIG_ENV_OVERWRITE
314
315#define CONFIG_NETDEV "eth1"
316
317#define CONFIG_HOSTNAME "mpc8313erdb"
318#define CONFIG_ROOTPATH "/nfs/root/path"
319#define CONFIG_BOOTFILE "uImage"
320
321#define CONFIG_UBOOTPATH "u-boot.bin"
322#define CONFIG_FDTFILE "mpc8313erdb.dtb"
323
324
325#define CONFIG_LOADADDR 800000
326
327#define CONFIG_EXTRA_ENV_SETTINGS \
328 "netdev=" CONFIG_NETDEV "\0" \
329 "ethprime=TSEC1\0" \
330 "uboot=" CONFIG_UBOOTPATH "\0" \
331 "tftpflash=tftpboot $loadaddr $uboot; " \
332 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
333 " +$filesize; " \
334 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
335 " +$filesize; " \
336 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
337 " $filesize; " \
338 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
339 " +$filesize; " \
340 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
341 " $filesize\0" \
342 "fdtaddr=780000\0" \
343 "fdtfile=" CONFIG_FDTFILE "\0" \
344 "console=ttyS0\0" \
345 "setbootargs=setenv bootargs " \
346 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
347 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
348 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
349 "$netdev:off " \
350 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
351
352#define CONFIG_NFSBOOTCOMMAND \
353 "setenv rootdev /dev/nfs;" \
354 "run setbootargs;" \
355 "run setipargs;" \
356 "tftp $loadaddr $bootfile;" \
357 "tftp $fdtaddr $fdtfile;" \
358 "bootm $loadaddr - $fdtaddr"
359
360#define CONFIG_RAMBOOTCOMMAND \
361 "setenv rootdev /dev/ram;" \
362 "run setbootargs;" \
363 "tftp $ramdiskaddr $ramdiskfile;" \
364 "tftp $loadaddr $bootfile;" \
365 "tftp $fdtaddr $fdtfile;" \
366 "bootm $loadaddr $ramdiskaddr $fdtaddr"
367
368#endif
369