1
2
3
4
5
6
7
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12
13
14
15#define CONFIG_E300 1
16
17
18
19
20#define CONFIG_SYS_SICRL 0x00000000
21
22
23
24
25#define CONFIG_SYS_SDRAM_BASE 0x00000000
26
27#undef CONFIG_SPD_EEPROM
28#if defined(CONFIG_SPD_EEPROM)
29
30
31#define SPD_EEPROM_ADDRESS 0x51
32#else
33
34
35#define CONFIG_SYS_DDR_SIZE 64
36#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
37 | CSCONFIG_ROW_BIT_13 \
38 | CSCONFIG_COL_BIT_9)
39
40#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
41 | (0 << TIMING_CFG0_WRT_SHIFT) \
42 | (0 << TIMING_CFG0_RRT_SHIFT) \
43 | (0 << TIMING_CFG0_WWT_SHIFT) \
44 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
45 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
46 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
47 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
48
49#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
50 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
51 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
52 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
53 | (3 << TIMING_CFG1_REFREC_SHIFT) \
54 | (2 << TIMING_CFG1_WRREC_SHIFT) \
55 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
56 | (2 << TIMING_CFG1_WRTORD_SHIFT))
57
58#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
59 | (31 << TIMING_CFG2_CPO_SHIFT) \
60 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
61 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
62 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
63 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
64 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
65
66#define CONFIG_SYS_DDR_TIMING_3 0x00000000
67#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
68
69#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
70 | (0x0232 << SDRAM_MODE_SD_SHIFT))
71
72#define CONFIG_SYS_DDR_MODE2 0x8000c000
73#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
74 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
75
76#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
77#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
78 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
79 | SDRAM_CFG_32_BE)
80
81#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
82#endif
83
84
85
86
87#undef CONFIG_SYS_DRAM_TEST
88#define CONFIG_SYS_MEMTEST_START 0x00030000
89#define CONFIG_SYS_MEMTEST_END 0x03f00000
90
91
92
93
94#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
95
96#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
97#define CONFIG_SYS_RAMBOOT
98#else
99#undef CONFIG_SYS_RAMBOOT
100#endif
101
102
103#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
104#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
105
106
107
108
109#define CONFIG_SYS_INIT_RAM_LOCK 1
110#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
111#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
112#define CONFIG_SYS_GBL_DATA_OFFSET \
113 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
114
115
116
117
118#define CONFIG_SYS_FLASH_BASE 0xFE000000
119#define CONFIG_SYS_FLASH_SIZE 16
120
121
122
123#define CONFIG_SYS_MAX_FLASH_BANKS 1
124#define CONFIG_SYS_MAX_FLASH_SECT 128
125
126#undef CONFIG_SYS_FLASH_CHECKSUM
127
128
129
130
131#define CONFIG_SYS_NS16550_SERIAL
132#define CONFIG_SYS_NS16550_REG_SIZE 1
133#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
134
135#define CONFIG_SYS_BAUDRATE_TABLE \
136 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
137
138#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
139#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
140
141
142#define CONFIG_SYS_I2C
143#define CONFIG_SYS_I2C_FSL
144#define CONFIG_SYS_FSL_I2C_SPEED 400000
145#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
146#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
147#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
148
149
150
151
152#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
153#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
154#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
155#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
156
157
158
159
160
161#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
162#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
163#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
164#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
165#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
166#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
167#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
168#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
169#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000
170
171#ifdef CONFIG_PCI
172#define CONFIG_PCI_INDIRECT_BRIDGE
173#define CONFIG_PCI_SKIP_HOST_BRIDGE
174
175#undef CONFIG_EEPRO100
176#undef CONFIG_PCI_SCAN_SHOW
177#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
178
179#endif
180
181
182
183
184#define CONFIG_UEC_ETH
185#define CONFIG_ETHPRIME "UEC0"
186
187#define CONFIG_UEC_ETH1
188
189#ifdef CONFIG_UEC_ETH1
190#define CONFIG_SYS_UEC1_UCC_NUM 2
191#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
192#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
193#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
194#define CONFIG_SYS_UEC1_PHY_ADDR 4
195#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
196#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
197#endif
198
199#define CONFIG_UEC_ETH2
200
201#ifdef CONFIG_UEC_ETH2
202#define CONFIG_SYS_UEC2_UCC_NUM 1
203#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
204#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
205#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
206#define CONFIG_SYS_UEC2_PHY_ADDR 0
207#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
208#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
209#endif
210
211
212
213
214
215#define CONFIG_LOADS_ECHO 1
216#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
217
218
219
220
221#define CONFIG_BOOTP_BOOTFILESIZE
222
223
224
225
226
227#undef CONFIG_WATCHDOG
228
229
230
231
232#define CONFIG_SYS_LOAD_ADDR 0x2000000
233
234
235
236
237
238
239
240#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
241#define CONFIG_SYS_BOOTM_LEN (64 << 20)
242
243#if (CONFIG_CMD_KGDB)
244#define CONFIG_KGDB_BAUDRATE 230400
245#endif
246
247
248
249
250#define CONFIG_ENV_OVERWRITE
251
252#define CONFIG_HAS_ETH0
253#define CONFIG_HAS_ETH1
254
255
256
257
258#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
259
260#define CONFIG_NETDEV "eth1"
261
262#define CONFIG_HOSTNAME "mpc8323erdb"
263#define CONFIG_ROOTPATH "/nfsroot"
264#define CONFIG_BOOTFILE "uImage"
265
266#define CONFIG_UBOOTPATH "u-boot.bin"
267#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
268#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
269
270
271#define CONFIG_LOADADDR 800000
272
273#define CONFIG_EXTRA_ENV_SETTINGS \
274 "netdev=" CONFIG_NETDEV "\0" \
275 "uboot=" CONFIG_UBOOTPATH "\0" \
276 "tftpflash=tftp $loadaddr $uboot;" \
277 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
278 " +$filesize; " \
279 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
280 " +$filesize; " \
281 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
282 " $filesize; " \
283 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
284 " +$filesize; " \
285 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
286 " $filesize\0" \
287 "fdtaddr=780000\0" \
288 "fdtfile=" CONFIG_FDTFILE "\0" \
289 "ramdiskaddr=1000000\0" \
290 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
291 "console=ttyS0\0" \
292 "setbootargs=setenv bootargs " \
293 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
294 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
295 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
296 "$netdev:off "\
297 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
298
299#define CONFIG_NFSBOOTCOMMAND \
300 "setenv rootdev /dev/nfs;" \
301 "run setbootargs;" \
302 "run setipargs;" \
303 "tftp $loadaddr $bootfile;" \
304 "tftp $fdtaddr $fdtfile;" \
305 "bootm $loadaddr - $fdtaddr"
306
307#define CONFIG_RAMBOOTCOMMAND \
308 "setenv rootdev /dev/ram;" \
309 "run setbootargs;" \
310 "tftp $ramdiskaddr $ramdiskfile;" \
311 "tftp $loadaddr $bootfile;" \
312 "tftp $fdtaddr $fdtfile;" \
313 "bootm $loadaddr $ramdiskaddr $fdtaddr"
314
315#endif
316