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17#ifndef __CONFIG_H
18#define __CONFIG_H
19
20
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22
23
24
25#ifndef CONFIG_HAS_FEC
26#define CONFIG_HAS_FEC 1
27#endif
28
29#define CONFIG_PCI_INDIRECT_BRIDGE
30#define CONFIG_SYS_PCI_64BIT 1
31#define CONFIG_ENV_OVERWRITE
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50
51#ifndef CONFIG_SYS_CLK_FREQ
52#define CONFIG_SYS_CLK_FREQ 33000000
53#endif
54
55
56
57
58#define CONFIG_L2_CACHE
59#define CONFIG_BTB
60
61#define CONFIG_SYS_MEMTEST_START 0x00200000
62#define CONFIG_SYS_MEMTEST_END 0x00400000
63
64#define CONFIG_SYS_CCSRBAR 0xe0000000
65#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
66
67
68#define CONFIG_SPD_EEPROM
69#define CONFIG_DDR_SPD
70
71#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
72
73#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
74#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
75
76#define CONFIG_DIMM_SLOTS_PER_CTLR 1
77#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
78
79
80#define SPD_EEPROM_ADDRESS 0x51
81
82
83#define CONFIG_SYS_SDRAM_SIZE 128
84#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
85#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
86#define CONFIG_SYS_DDR_TIMING_1 0x37344321
87#define CONFIG_SYS_DDR_TIMING_2 0x00000800
88#define CONFIG_SYS_DDR_CONTROL 0xc2000000
89#define CONFIG_SYS_DDR_MODE 0x00000062
90#define CONFIG_SYS_DDR_INTERVAL 0x05200100
91
92
93
94
95#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
96#define CONFIG_SYS_LBC_SDRAM_SIZE 64
97
98#define CONFIG_SYS_FLASH_BASE 0xff000000
99#define CONFIG_SYS_BR0_PRELIM 0xff001801
100
101#define CONFIG_SYS_OR0_PRELIM 0xff006ff7
102#define CONFIG_SYS_MAX_FLASH_BANKS 1
103#define CONFIG_SYS_MAX_FLASH_SECT 64
104#undef CONFIG_SYS_FLASH_CHECKSUM
105#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
106#define CONFIG_SYS_FLASH_WRITE_TOUT 500
107
108#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
109
110#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
111#define CONFIG_SYS_RAMBOOT
112#else
113#undef CONFIG_SYS_RAMBOOT
114#endif
115
116#define CONFIG_SYS_FLASH_EMPTY_INFO
117
118#undef CONFIG_CLOCKS_IN_MHZ
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141
142#define CONFIG_SYS_BR2_PRELIM 0xf0001861
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157
158#define CONFIG_SYS_OR2_PRELIM 0xfc006901
159
160#define CONFIG_SYS_LBC_LCRR 0x00030004
161#define CONFIG_SYS_LBC_LBCR 0x00000000
162#define CONFIG_SYS_LBC_LSRT 0x20000000
163#define CONFIG_SYS_LBC_MRTPR 0x20000000
164
165#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
166 | LSDMR_RFCR5 \
167 | LSDMR_PRETOACT3 \
168 | LSDMR_ACTTORW3 \
169 | LSDMR_BL8 \
170 | LSDMR_WRC2 \
171 | LSDMR_CL3 \
172 | LSDMR_RFEN \
173 )
174
175
176
177
178#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
179#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
180#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
181#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
182#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
183
184
185
186
187#define CONFIG_SYS_BR4_PRELIM 0xf8000801
188#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
189#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
190
191#define CONFIG_SYS_INIT_RAM_LOCK 1
192#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
193#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
194
195#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
196#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
197
198#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
199#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
200
201
202#define CONFIG_SYS_NS16550_SERIAL
203#define CONFIG_SYS_NS16550_REG_SIZE 1
204#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
205
206#define CONFIG_SYS_BAUDRATE_TABLE \
207 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
208
209#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
210#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
211
212
213
214
215#define CONFIG_SYS_I2C
216#define CONFIG_SYS_I2C_FSL
217#define CONFIG_SYS_FSL_I2C_SPEED 400000
218#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
219#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
220#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
221
222
223#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000
224#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000
225#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
226#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000
227
228
229
230
231
232#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
233#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
234#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
235#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
236#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
237#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
238#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
239#define CONFIG_SYS_PCI1_IO_SIZE 0x100000
240
241#if defined(CONFIG_PCI)
242#undef CONFIG_EEPRO100
243#undef CONFIG_TULIP
244
245#if !defined(CONFIG_PCI_PNP)
246 #define PCI_ENET0_IOADDR 0xe0000000
247 #define PCI_ENET0_MEMADDR 0xe0000000
248 #define PCI_IDSEL_NUMBER 0x0c
249#endif
250
251#undef CONFIG_PCI_SCAN_SHOW
252#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
253
254#endif
255
256#if defined(CONFIG_TSEC_ENET)
257
258#define CONFIG_TSEC1 1
259#define CONFIG_TSEC1_NAME "TSEC0"
260#define CONFIG_TSEC2 1
261#define CONFIG_TSEC2_NAME "TSEC1"
262#define TSEC1_PHY_ADDR 0
263#define TSEC2_PHY_ADDR 1
264#define TSEC1_PHYIDX 0
265#define TSEC2_PHYIDX 0
266#define TSEC1_FLAGS TSEC_GIGABIT
267#define TSEC2_FLAGS TSEC_GIGABIT
268
269#if CONFIG_HAS_FEC
270#define CONFIG_MPC85XX_FEC 1
271#define CONFIG_MPC85XX_FEC_NAME "FEC"
272#define FEC_PHY_ADDR 3
273#define FEC_PHYIDX 0
274#define FEC_FLAGS 0
275#endif
276
277
278#define CONFIG_ETHPRIME "TSEC0"
279
280#endif
281
282
283
284
285
286#define CONFIG_LOADS_ECHO 1
287#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
288
289
290
291
292#define CONFIG_BOOTP_BOOTFILESIZE
293
294
295
296
297
298#undef CONFIG_WATCHDOG
299
300
301
302
303#define CONFIG_SYS_LOAD_ADDR 0x2000000
304
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308
309
310#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
311#define CONFIG_SYS_BOOTM_LEN (64 << 20)
312
313#if defined(CONFIG_CMD_KGDB)
314#define CONFIG_KGDB_BAUDRATE 230400
315#endif
316
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320
321
322#if defined(CONFIG_TSEC_ENET)
323#define CONFIG_HAS_ETH0
324#define CONFIG_HAS_ETH1
325#define CONFIG_HAS_ETH2
326#endif
327
328#define CONFIG_IPADDR 192.168.1.253
329
330#define CONFIG_HOSTNAME "unknown"
331#define CONFIG_ROOTPATH "/nfsroot"
332#define CONFIG_BOOTFILE "your.uImage"
333
334#define CONFIG_SERVERIP 192.168.1.1
335#define CONFIG_GATEWAYIP 192.168.1.1
336#define CONFIG_NETMASK 255.255.255.0
337
338#define CONFIG_LOADADDR 200000
339
340#define CONFIG_EXTRA_ENV_SETTINGS \
341 "netdev=eth0\0" \
342 "consoledev=ttyS0\0" \
343 "ramdiskaddr=1000000\0" \
344 "ramdiskfile=your.ramdisk.u-boot\0" \
345 "fdtaddr=400000\0" \
346 "fdtfile=your.fdt.dtb\0"
347
348#define CONFIG_NFSBOOTCOMMAND \
349 "setenv bootargs root=/dev/nfs rw " \
350 "nfsroot=$serverip:$rootpath " \
351 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
352 "console=$consoledev,$baudrate $othbootargs;" \
353 "tftp $loadaddr $bootfile;" \
354 "tftp $fdtaddr $fdtfile;" \
355 "bootm $loadaddr - $fdtaddr"
356
357#define CONFIG_RAMBOOTCOMMAND \
358 "setenv bootargs root=/dev/ram rw " \
359 "console=$consoledev,$baudrate $othbootargs;" \
360 "tftp $ramdiskaddr $ramdiskfile;" \
361 "tftp $loadaddr $bootfile;" \
362 "tftp $fdtaddr $fdtfile;" \
363 "bootm $loadaddr $ramdiskaddr $fdtaddr"
364
365#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
366
367#endif
368