LXR uboot/include/configs/capricorn-common.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2017-2018 NXP
   4 * Copyright 2019 Siemens AG
   5 */
   6
   7#ifndef __IMX8X_CAPRICORN_H
   8#define __IMX8X_CAPRICORN_H
   9
  10#include <linux/sizes.h>
  11#include <asm/arch/imx-regs.h>
  12
  13#include "siemens-env-common.h"
  14#include "siemens-ccp-common.h"
  15
  16/* SPL config */
  17#ifdef CONFIG_SPL_BUILD
  18
  19#define CONFIG_SPL_MAX_SIZE             (124 * 1024)
  20#define CONFIG_SYS_MONITOR_LEN          (1024 * 1024)
  21#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  22#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0x800
  23#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION              0
  24
  25#define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  26#define CONFIG_SPL_STACK                0x013E000
  27#define CONFIG_SPL_BSS_START_ADDR       0x00128000
  28#define CONFIG_SPL_BSS_MAX_SIZE         0x1000  /* 4 KB */
  29#define CONFIG_SYS_SPL_MALLOC_START     0x00120000
  30#define CONFIG_SYS_SPL_MALLOC_SIZE      0x3000  /* 12 KB */
  31#define CONFIG_MALLOC_F_ADDR            0x00120000
  32
  33#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
  34#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  35
  36#endif /* CONFIG_SPL_BUILD */
  37
  38#define CONFIG_FACTORYSET
  39
  40#undef CONFIG_IDENT_STRING
  41#define CONFIG_IDENT_STRING             GENERATE_CCP_VERSION("01", "07")
  42
  43#define CONFIG_REMAKE_ELF
  44
  45#define CONFIG_BOARD_EARLY_INIT_F
  46
  47/* Commands */
  48#define CONFIG_CMD_READ
  49
  50#undef CONFIG_CMD_EXPORTENV
  51#undef CONFIG_CMD_IMPORTENV
  52#undef CONFIG_CMD_IMLS
  53#undef CONFIG_CMD_CRC32
  54#undef CONFIG_BOOTM_NETBSD
  55
  56/* ENET Config */
  57#define CONFIG_FEC_XCV_TYPE             RMII
  58#define FEC_QUIRK_ENET_MAC
  59
  60/* ENET1 connects to base board and MUX with ESAI */
  61#define CONFIG_FEC_ENET_DEV             1
  62#define CONFIG_FEC_MXC_PHYADDR          0x0
  63#define CONFIG_ETHPRIME                "eth1"
  64
  65/* I2C Configuration */
  66#ifndef CONFIG_SPL_BUILD
  67#define CONFIG_SYS_I2C_SPEED    400000
  68/* EEPROM */
  69#define  EEPROM_I2C_BUS         0 /* I2C0 */
  70#define  EEPROM_I2C_ADDR        0x50
  71/* PCA9552 */
  72#define  PCA9552_1_I2C_BUS      1 /* I2C1 */
  73#define  PCA9552_1_I2C_ADDR     0x60
  74#endif /* !CONFIG_SPL_BUILD */
  75
  76/* AHAB */
  77#ifdef CONFIG_AHAB_BOOT
  78#define AHAB_ENV "sec_boot=yes\0"
  79#else
  80#define AHAB_ENV "sec_boot=no\0"
  81#endif
  82
  83#define MFG_ENV_SETTINGS_DEFAULT \
  84        "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  85                "rdinit=/linuxrc " \
  86                "clk_ignore_unused "\
  87                "\0" \
  88        "kboot=booti\0"\
  89        "bootcmd_mfg=run mfgtool_args;" \
  90        "if iminfo ${initrd_addr}; then " \
  91        "if test ${tee} = yes; then " \
  92                "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
  93        "else " \
  94                "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
  95        "fi; " \
  96        "else " \
  97            "echo \"Run fastboot ...\"; fastboot 0; "  \
  98        "fi;\0"
  99
 100/* Boot M4 */
 101#define M4_BOOT_ENV \
 102        "m4_0_image=m4_0.bin\0" \
 103        "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
 104                        "${loadaddr} ${m4_0_image}\0" \
 105        "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
 106
 107#define CONFIG_MFG_ENV_SETTINGS \
 108        MFG_ENV_SETTINGS_DEFAULT \
 109        "initrd_addr=0x83100000\0" \
 110        "initrd_high=0xffffffffffffffff\0" \
 111        "emmc_dev=0\0"
 112
 113/* Initial environment variables */
 114#define CONFIG_EXTRA_ENV_SETTINGS \
 115        CONFIG_MFG_ENV_SETTINGS \
 116        M4_BOOT_ENV \
 117        AHAB_ENV \
 118        ENV_COMMON \
 119        "script=boot.scr\0" \
 120        "image=Image\0" \
 121        "panel=NULL\0" \
 122        "console=ttyLP2\0" \
 123        "fdt_addr=0x83000000\0" \
 124        "fdt_high=0xffffffffffffffff\0" \
 125        "cntr_addr=0x88000000\0" \
 126        "cntr_file=os_cntr_signed.bin\0" \
 127        "initrd_addr=0x83800000\0" \
 128        "initrd_high=0xffffffffffffffff\0" \
 129        "netdev=eth0\0" \
 130        "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
 131        "hostname=capricorn\0" \
 132        ENV_EMMC \
 133        ENV_NET
 134
 135#define CONFIG_BOOTCOMMAND \
 136        "if usrbutton; then " \
 137                "run flash_self_test; " \
 138                "reset; " \
 139        "fi;" \
 140        "run flash_self;" \
 141        "reset;"
 142
 143/* Default location for tftp and bootm */
 144#define CONFIG_LOADADDR                 0x80280000
 145#define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
 146#define CONFIG_SYS_INIT_SP_ADDR         0x80200000
 147
 148#define CONFIG_BOOTCOUNT_LIMIT
 149#define CONFIG_BOOTCOUNT_ENV
 150
 151/* Environment organisation */
 152#define CONFIG_ENV_OVERWRITE
 153#define CONFIG_SYS_MMC_ENV_DEV          0       /* USDHC1, eMMC */
 154#define CONFIG_SYS_MMC_ENV_PART         2       /* 2nd boot partition */
 155
 156/* On CCP board, USDHC1 is for eMMC */
 157#define CONFIG_MMCROOT                  "/dev/mmcblk0p2"  /* eMMC */
 158#define CONFIG_SYS_MMC_IMG_LOAD_PART    1
 159
 160/* Size of malloc() pool */
 161#define CONFIG_SYS_MALLOC_LEN           ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
 162
 163#define CONFIG_SYS_SDRAM_BASE           0x80000000
 164#define PHYS_SDRAM_1                    0x80000000
 165#define PHYS_SDRAM_2                    0x880000000
 166/* DDR3 board total DDR is 1 GB */
 167#define PHYS_SDRAM_1_SIZE               0x40000000      /* 1 GB */
 168#define PHYS_SDRAM_2_SIZE               0x00000000      /* 0 GB */
 169
 170#define CONFIG_SYS_MEMTEST_START        0xA0000000
 171#define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 172                                         (PHYS_SDRAM_1_SIZE >> 2))
 173
 174/* Console buffer and boot args */
 175#define CONFIG_SYS_CBSIZE               2048
 176#define CONFIG_SYS_MAXARGS              64
 177#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 178
 179/* Generic Timer Definitions */
 180#define COUNTER_FREQUENCY               8000000 /* 8MHz */
 181
 182#define BOOTAUX_RESERVED_MEM_BASE       0x88000000
 183#define BOOTAUX_RESERVED_MEM_SIZE       SZ_128M /* Reserve from second 128MB */
 184
 185#endif /* __IMX8X_CAPRICORN_H */
 186