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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14
15
16
17#define CONFIG_BOOT_RETRY_TIME 900
18#define CONFIG_BOOT_RETRY_MIN 30
19#define CONFIG_RESET_TO_RETRY
20
21#define CONFIG_SYS_SICRH 0x00000000
22#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
23
24#define CONFIG_HWCONFIG
25
26
27
28
29#define CONFIG_SYS_INIT_RAM_LOCK
30#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
31#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
32#define CONFIG_SYS_GBL_DATA_SIZE 0x100
33#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
34 - CONFIG_SYS_GBL_DATA_SIZE)
35#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
36
37
38
39
40
41
42
43#define CONFIG_SYS_SDRAM_BASE 0x00000000
44
45
46
47
48
49#define CONFIG_SYS_DDR_SIZE 256
50#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
51 0x00010000 |\
52 CSCONFIG_ROW_BIT_13 |\
53 CSCONFIG_COL_BIT_10)
54
55#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
56 CSCONFIG_BANK_BIT_3)
57
58#define CONFIG_SYS_DDR_TIMING_3 (1 << 16)
59#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
60 (3 << TIMING_CFG0_WRT_SHIFT) |\
61 (3 << TIMING_CFG0_RRT_SHIFT) |\
62 (3 << TIMING_CFG0_WWT_SHIFT) |\
63 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
64 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
65 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
66 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
67#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
68 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
69 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
70 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
71 (4 << TIMING_CFG1_REFREC_SHIFT) |\
72 (4 << TIMING_CFG1_WRREC_SHIFT) |\
73 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
74 (2 << TIMING_CFG1_WRTORD_SHIFT))
75#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
76 (5 << TIMING_CFG2_CPO_SHIFT) |\
77 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
78 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
79 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
80 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
81 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
82
83#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
84 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
85
86#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
87 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
88 SDRAM_CFG_DBW_32 |\
89 SDRAM_CFG_SDRAM_TYPE_DDR2)
90
91#define CONFIG_SYS_SDRAM_CFG2 0x00401000
92#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
93 (0x0242 << SDRAM_MODE_SD_SHIFT))
94#define CONFIG_SYS_DDR_MODE_2 0x00000000
95#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
96#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
97 DDRCDR_PZ_NOMZ |\
98 DDRCDR_NZ_NOMZ |\
99 DDRCDR_ODT |\
100 DDRCDR_M_ODR |\
101 DDRCDR_Q_DRN)
102
103
104
105
106#define CONFIG_TSEC1
107#define CONFIG_TSEC2
108
109
110
111
112#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
113#define CONFIG_FLASH_SHOW_PROGRESS 50
114
115#define CONFIG_SYS_FLASH_BASE 0xFF800000
116#define CONFIG_SYS_FLASH_SIZE 8
117
118
119#define CONFIG_SYS_MAX_FLASH_BANKS 1
120#define CONFIG_SYS_MAX_FLASH_SECT 128
121
122#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
123#define CONFIG_SYS_FLASH_WRITE_TOUT 500
124
125
126
127
128#define CONFIG_SYS_NAND_BASE 0xE1000000
129#define CONFIG_SYS_MAX_NAND_DEVICE 1
130#define CONFIG_SYS_NAND_MAX_CHIPS 1
131#define CONFIG_NAND_FSL_ELBC
132#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
133#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
134#define NAND_CACHE_PAGES 64
135
136
137
138
139
140#define CONFIG_SYS_MRAM_BASE 0xE2000000
141#define CONFIG_SYS_MRAM_SIZE 0x20000
142
143#define CONFIG_SYS_OR_TIMING_MRAM
144
145
146
147
148
149#define CONFIG_SYS_CPLD_BASE 0xE3000000
150#define CONFIG_SYS_CPLD_SIZE 0x8000
151
152#define CONFIG_SYS_OR_TIMING_MRAM
153
154
155
156
157
158#define CONFIG_WATCHDOG 1
159#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
160
161
162
163
164#define CONFIG_SYS_I2C
165#define CONFIG_SYS_I2C_FSL
166#define CONFIG_SYS_FSL_I2C_SPEED 400000
167#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
168#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
169#define CONFIG_RTC_PCF8563
170#define CONFIG_SYS_I2C_RTC_ADDR 0x51
171
172
173
174
175#ifdef CONFIG_TSEC1
176#define CONFIG_HAS_ETH0
177#define CONFIG_TSEC1_NAME "TSEC0"
178#define CONFIG_SYS_TSEC1_OFFSET 0x24000
179#define TSEC1_PHY_ADDR 0x1
180#define TSEC1_FLAGS TSEC_GIGABIT
181#define TSEC1_PHYIDX 0
182#endif
183
184#ifdef CONFIG_TSEC2
185#define CONFIG_HAS_ETH1
186#define CONFIG_TSEC2_NAME "TSEC1"
187#define CONFIG_SYS_TSEC2_OFFSET 0x25000
188#define TSEC2_PHY_ADDR 0x3
189#define TSEC2_FLAGS TSEC_GIGABIT
190#define TSEC2_PHYIDX 0
191#endif
192#define CONFIG_ETHPRIME "TSEC1"
193
194
195
196
197#define CONFIG_SYS_NS16550_SERIAL
198#define CONFIG_SYS_NS16550_REG_SIZE 1
199
200#define CONFIG_SYS_BAUDRATE_TABLE \
201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
202#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
203#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
204#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
205
206#define CONFIG_HAS_FSL_DR_USB
207#define CONFIG_SYS_SCCR_USBDRCM 3
208
209
210
211
212#define CONFIG_BOOTP_BOOTFILESIZE
213
214
215
216
217#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
218#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
219#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
220
221
222
223
224
225#define CONFIG_NETDEV eth1
226#define CONFIG_HOSTNAME "ids8313"
227#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
228#define CONFIG_BOOTFILE "ids8313/uImage"
229#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
230#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
231#define CONFIG_LOADADDR 0x400000
232#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
233
234
235#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
236
237
238
239
240#define CONFIG_SYS_CBSIZE 1024
241#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
242
243#define CONFIG_SYS_MEMTEST_START 0x00001000
244#define CONFIG_SYS_MEMTEST_END 0x00C00000
245
246#define CONFIG_SYS_LOAD_ADDR 0x100000
247#define CONFIG_LOADS_ECHO
248#define CONFIG_TIMESTAMP
249#define CONFIG_BOOTCOMMAND "run boot_cramfs"
250#undef CONFIG_SYS_LOADS_BAUD_CHANGE
251
252#define CONFIG_JFFS2_NAND
253#define CONFIG_JFFS2_DEV "0"
254
255
256
257#define CONFIG_EXTRA_ENV_SETTINGS \
258 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
259 "ethprime=TSEC1\0" \
260 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
261 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
262 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
263 " +${filesize}; " \
264 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
265 " +${filesize}; " \
266 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
267 " ${filesize}; " \
268 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
269 " +${filesize}; " \
270 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
271 " ${filesize}\0" \
272 "console=ttyS0\0" \
273 "fdtaddr=0x780000\0" \
274 "kernel_addr=ff800000\0" \
275 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
276 "setbootargs=setenv bootargs " \
277 "root=${rootdev} rw console=${console}," \
278 "${baudrate} ${othbootargs}\0" \
279 "setipargs=setenv bootargs root=${rootdev} rw " \
280 "nfsroot=${serverip}:${rootpath} " \
281 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
282 "${netmask}:${hostname}:${netdev}:off " \
283 "console=${console},${baudrate} ${othbootargs}\0" \
284 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
285 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
286 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
287 "\0"
288
289#define CONFIG_NFSBOOTCOMMAND \
290 "setenv rootdev /dev/nfs;" \
291 "run setipargs;run addmtd;" \
292 "tftp ${loadaddr} ${bootfile};" \
293 "tftp ${fdtaddr} ${fdtfile};" \
294 "fdt addr ${fdtaddr};" \
295 "bootm ${loadaddr} - ${fdtaddr}"
296
297
298
299#endif
300
