1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2017, 2019-2020 NXP 4 * Copyright 2015 Freescale Semiconductor 5 */ 6 7#ifndef __LS2_QDS_H 8#define __LS2_QDS_H 9 10#include "ls2080a_common.h" 11 12#ifndef __ASSEMBLY__ 13unsigned long get_board_sys_clk(void); 14unsigned long get_board_ddr_clk(void); 15#endif 16 17#ifdef CONFIG_FSL_QSPI 18#define CONFIG_QIXIS_I2C_ACCESS 19#ifndef CONFIG_DM_I2C 20#define CONFIG_SYS_I2C_EARLY_INIT 21#endif 22#define CONFIG_SYS_I2C_IFDR_DIV 0x7e 23#endif 24 25#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 26#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 27#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 28#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 29 30#define CONFIG_DDR_SPD 31#define CONFIG_DDR_ECC 32#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 33#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 34#define SPD_EEPROM_ADDRESS1 0x51 35#define SPD_EEPROM_ADDRESS2 0x52 36#define SPD_EEPROM_ADDRESS3 0x53 37#define SPD_EEPROM_ADDRESS4 0x54 38#define SPD_EEPROM_ADDRESS5 0x55 39#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 40#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 41#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 42#define CONFIG_DIMM_SLOTS_PER_CTLR 2 43#define CONFIG_CHIP_SELECTS_PER_CTRL 4 44#ifdef CONFIG_SYS_FSL_HAS_DP_DDR 45#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 46#endif 47 48/* SATA */ 49#define CONFIG_SCSI_AHCI_PLAT 50 51#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 52#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 53 54#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 55#define CONFIG_SYS_SCSI_MAX_LUN 1 56#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 57 CONFIG_SYS_SCSI_MAX_LUN) 58 59#ifdef CONFIG_TFABOOT 60#define CONFIG_SYS_MMC_ENV_DEV 0 61#endif 62 63#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 64#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 65#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 66 67#define CONFIG_SYS_NOR0_CSPR \ 68 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 69 CSPR_PORT_SIZE_16 | \ 70 CSPR_MSEL_NOR | \ 71 CSPR_V) 72#define CONFIG_SYS_NOR0_CSPR_EARLY \ 73 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 74 CSPR_PORT_SIZE_16 | \ 75 CSPR_MSEL_NOR | \ 76 CSPR_V) 77#define CONFIG_SYS_NOR1_CSPR \ 78 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 79 CSPR_PORT_SIZE_16 | \ 80 CSPR_MSEL_NOR | \ 81 CSPR_V) 82#define CONFIG_SYS_NOR1_CSPR_EARLY \ 83 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 84 CSPR_PORT_SIZE_16 | \ 85 CSPR_MSEL_NOR | \ 86 CSPR_V) 87#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 88#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 89 FTIM0_NOR_TEADC(0x5) | \ 90 FTIM0_NOR_TEAHC(0x5)) 91#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 92 FTIM1_NOR_TRAD_NOR(0x1a) |\ 93 FTIM1_NOR_TSEQRAD_NOR(0x13)) 94#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 95 FTIM2_NOR_TCH(0x4) | \ 96 FTIM2_NOR_TWPH(0x0E) | \ 97 FTIM2_NOR_TWP(0x1c)) 98#define CONFIG_SYS_NOR_FTIM3 0x04000000 99#define CONFIG_SYS_IFC_CCR 0x01000000 100 101#ifdef CONFIG_MTD_NOR_FLASH 102#define CONFIG_SYS_FLASH_QUIET_TEST 103#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 104 105#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 106#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 107#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 108#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 109 110#define CONFIG_SYS_FLASH_EMPTY_INFO 111#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 112 CONFIG_SYS_FLASH_BASE + 0x40000000} 113#endif 114 115#define CONFIG_NAND_FSL_IFC 116#define CONFIG_SYS_NAND_MAX_ECCPOS 256 117#define CONFIG_SYS_NAND_MAX_OOBFREE 2 118 119#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 120#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 121 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 122 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 123 | CSPR_V) 124#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 125 126#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 127 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 128 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 129 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 130 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 131 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 132 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 133 134#define CONFIG_SYS_NAND_ONFI_DETECTION 135 136/* ONFI NAND Flash mode0 Timing Params */ 137#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 138 FTIM0_NAND_TWP(0x18) | \ 139 FTIM0_NAND_TWCHT(0x07) | \ 140 FTIM0_NAND_TWH(0x0a)) 141#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 142 FTIM1_NAND_TWBE(0x39) | \ 143 FTIM1_NAND_TRR(0x0e) | \ 144 FTIM1_NAND_TRP(0x18)) 145#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 146 FTIM2_NAND_TREH(0x0a) | \ 147 FTIM2_NAND_TWHRE(0x1e)) 148#define CONFIG_SYS_NAND_FTIM3 0x0 149 150#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 151#define CONFIG_SYS_MAX_NAND_DEVICE 1 152#define CONFIG_MTD_NAND_VERIFY_WRITE 153 154#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 155 156#define CONFIG_FSL_QIXIS /* use common QIXIS code */ 157#define QIXIS_LBMAP_SWITCH 0x06 158#define QIXIS_LBMAP_MASK 0x0f 159#define QIXIS_LBMAP_SHIFT 0 160#define QIXIS_LBMAP_DFLTBANK 0x00 161#define QIXIS_LBMAP_ALTBANK 0x04 162#define QIXIS_LBMAP_NAND 0x09 163#define QIXIS_LBMAP_SD 0x00 164#define QIXIS_LBMAP_QSPI 0x0f 165#define QIXIS_RST_CTL_RESET 0x31 166#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 167#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 168#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 169#define QIXIS_RCW_SRC_NAND 0x107 170#define QIXIS_RCW_SRC_SD 0x40 171#define QIXIS_RCW_SRC_QSPI 0x62 172#define QIXIS_RST_FORCE_MEM 0x01 173 174#define CONFIG_SYS_CSPR3_EXT (0x0) 175#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 176 | CSPR_PORT_SIZE_8 \ 177 | CSPR_MSEL_GPCM \ 178 | CSPR_V) 179#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 180 | CSPR_PORT_SIZE_8 \ 181 | CSPR_MSEL_GPCM \ 182 | CSPR_V) 183 184#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 185#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 186/* QIXIS Timing parameters for IFC CS3 */ 187#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 188 FTIM0_GPCM_TEADC(0x0e) | \ 189 FTIM0_GPCM_TEAHC(0x0e)) 190#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 191 FTIM1_GPCM_TRAD(0x3f)) 192#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 193 FTIM2_GPCM_TCH(0xf) | \ 194 FTIM2_GPCM_TWP(0x3E)) 195#define CONFIG_SYS_CS3_FTIM3 0x0 196 197#if defined(CONFIG_SPL) 198#if defined(CONFIG_NAND_BOOT) 199#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 200#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 201#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 202#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 203#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 204#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 205#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 206#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 207#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 208#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 209#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 210#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 211#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 212#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 213#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 214#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 215#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 216#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 217#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 218#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 219#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 220#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 221#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 222#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 223#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 224#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 225#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 226 227#define CONFIG_SPL_PAD_TO 0x20000 228#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 229#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 230#elif defined(CONFIG_SD_BOOT) 231#define CONFIG_SYS_MMC_ENV_DEV 0 232#endif 233#else 234#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 235#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 236#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 237#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 238#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 239#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 240#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 241#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 242#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 243#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 244#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 245#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 246#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 247#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 248#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 249#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 250#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 251#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 252#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 253#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 254#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 255#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 256#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 257#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 258#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 259#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 260#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 261#endif 262 263/* Debug Server firmware */ 264#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 265#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 266 267#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 268 269/* 270 * I2C 271 */ 272#define I2C_MUX_PCA_ADDR 0x77 273#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 274 275/* I2C bus multiplexer */ 276#define I2C_MUX_CH_DEFAULT 0x8 277 278/* SPI */ 279#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 280#ifdef CONFIG_FSL_DSPI 281#define CONFIG_SPI_FLASH_STMICRO 282#define CONFIG_SPI_FLASH_SST 283#define CONFIG_SPI_FLASH_EON 284#endif 285 286#ifdef CONFIG_FSL_QSPI 287#define CONFIG_SPI_FLASH_SPANSION 288#define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ 289#define FSL_QSPI_FLASH_NUM 4 290#endif 291/* 292 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 293 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 294 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 295 */ 296#define FSL_QIXIS_BRDCFG9_QSPI 0x1 297 298#endif 299 300/* 301 * MMC 302 */ 303#ifdef CONFIG_MMC 304#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 305 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 306#endif 307 308/* 309 * RTC configuration 310 */ 311#define RTC 312#define CONFIG_RTC_DS3231 1 313#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT 314#define CONFIG_SYS_I2C_RTC_ADDR 0x68 315#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT 316 317/* EEPROM */ 318#define CONFIG_ID_EEPROM 319#define CONFIG_SYS_I2C_EEPROM_NXID 320#define CONFIG_SYS_EEPROM_BUS_NUM 0 321#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 322#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 323#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 324#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 325 326#define CONFIG_FSL_MEMAC 327 328#ifdef CONFIG_PCI 329#define CONFIG_PCI_SCAN_SHOW 330#endif 331 332/* MMC */ 333#ifdef CONFIG_MMC 334#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 335#endif 336 337/* Initial environment variables */ 338#undef CONFIG_EXTRA_ENV_SETTINGS 339#ifdef CONFIG_NXP_ESBC 340#define CONFIG_EXTRA_ENV_SETTINGS \ 341 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 342 "loadaddr=0x80100000\0" \ 343 "kernel_addr=0x100000\0" \ 344 "ramdisk_addr=0x800000\0" \ 345 "ramdisk_size=0x2000000\0" \ 346 "fdt_high=0xa0000000\0" \ 347 "initrd_high=0xffffffffffffffff\0" \ 348 "kernel_start=0x581000000\0" \ 349 "kernel_load=0xa0000000\0" \ 350 "kernel_size=0x2800000\0" \ 351 "mcmemsize=0x40000000\0" \ 352 "mcinitcmd=esbc_validate 0x580640000;" \ 353 "esbc_validate 0x580680000;" \ 354 "fsl_mc start mc 0x580a00000" \ 355 " 0x580e00000 \0" 356#else 357#ifdef CONFIG_TFABOOT 358#define SD_MC_INIT_CMD \ 359 "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ 360 "mmc read 0x80e00000 0x7000 0x800;" \ 361 "fsl_mc start mc 0x80a00000 0x80e00000\0" 362#define IFC_MC_INIT_CMD \ 363 "fsl_mc start mc 0x580a00000" \ 364 " 0x580e00000 \0" 365#define CONFIG_EXTRA_ENV_SETTINGS \ 366 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 367 "loadaddr=0x80100000\0" \ 368 "loadaddr_sd=0x90100000\0" \ 369 "kernel_addr=0x581000000\0" \ 370 "kernel_addr_sd=0x8000\0" \ 371 "ramdisk_addr=0x800000\0" \ 372 "ramdisk_size=0x2000000\0" \ 373 "fdt_high=0xa0000000\0" \ 374 "initrd_high=0xffffffffffffffff\0" \ 375 "kernel_start=0x581000000\0" \ 376 "kernel_start_sd=0x8000\0" \ 377 "kernel_load=0xa0000000\0" \ 378 "kernel_size=0x2800000\0" \ 379 "kernel_size_sd=0x14000\0" \ 380 "load_addr=0xa0000000\0" \ 381 "kernelheader_addr=0x580600000\0" \ 382 "kernelheader_addr_r=0x80200000\0" \ 383 "kernelheader_size=0x40000\0" \ 384 "BOARD=ls2088aqds\0" \ 385 "mcmemsize=0x70000000 \0" \ 386 "scriptaddr=0x80000000\0" \ 387 "scripthdraddr=0x80080000\0" \ 388 IFC_MC_INIT_CMD \ 389 BOOTENV \ 390 "boot_scripts=ls2088aqds_boot.scr\0" \ 391 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \ 392 "scan_dev_for_boot_part=" \ 393 "part list ${devtype} ${devnum} devplist; " \ 394 "env exists devplist || setenv devplist 1; " \ 395 "for distro_bootpart in ${devplist}; do " \ 396 "if fstype ${devtype} " \ 397 "${devnum}:${distro_bootpart} " \ 398 "bootfstype; then " \ 399 "run scan_dev_for_boot; " \ 400 "fi; " \ 401 "done\0" \ 402 "boot_a_script=" \ 403 "load ${devtype} ${devnum}:${distro_bootpart} " \ 404 "${scriptaddr} ${prefix}${script}; " \ 405 "env exists secureboot && load ${devtype} " \ 406 "${devnum}:${distro_bootpart} " \ 407 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 408 "&& esbc_validate ${scripthdraddr};" \ 409 "source ${scriptaddr}\0" \ 410 "nor_bootcmd=echo Trying load from nor..;" \ 411 "cp.b $kernel_addr $load_addr " \ 412 "$kernel_size ; env exists secureboot && " \ 413 "cp.b $kernelheader_addr $kernelheader_addr_r " \ 414 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 415 "bootm $load_addr#$BOARD\0" \ 416 "sd_bootcmd=echo Trying load from SD ..;" \ 417 "mmcinfo; mmc read $load_addr " \ 418 "$kernel_addr_sd $kernel_size_sd && " \ 419 "bootm $load_addr#$BOARD\0" 420#elif defined(CONFIG_SD_BOOT) 421#define CONFIG_EXTRA_ENV_SETTINGS \ 422 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 423 "loadaddr=0x90100000\0" \ 424 "kernel_addr=0x800\0" \ 425 "ramdisk_addr=0x800000\0" \ 426 "ramdisk_size=0x2000000\0" \ 427 "fdt_high=0xa0000000\0" \ 428 "initrd_high=0xffffffffffffffff\0" \ 429 "kernel_start=0x8000\0" \ 430 "kernel_load=0xa0000000\0" \ 431 "kernel_size=0x14000\0" \ 432 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 433 "mmc read 0x80100000 0x7000 0x800;" \ 434 "fsl_mc start mc 0x80000000 0x80100000\0" \ 435 "mcmemsize=0x70000000 \0" 436#else 437#define CONFIG_EXTRA_ENV_SETTINGS \ 438 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 439 "loadaddr=0x80100000\0" \ 440 "kernel_addr=0x100000\0" \ 441 "ramdisk_addr=0x800000\0" \ 442 "ramdisk_size=0x2000000\0" \ 443 "fdt_high=0xa0000000\0" \ 444 "initrd_high=0xffffffffffffffff\0" \ 445 "kernel_start=0x581000000\0" \ 446 "kernel_load=0xa0000000\0" \ 447 "kernel_size=0x2800000\0" \ 448 "mcmemsize=0x40000000\0" \ 449 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 450 " 0x580e00000 \0" 451#endif /* CONFIG_TFABOOT */ 452#endif /* CONFIG_NXP_ESBC */ 453 454#ifdef CONFIG_TFABOOT 455#define BOOT_TARGET_DEVICES(func) \ 456 func(USB, usb, 0) \ 457 func(MMC, mmc, 0) \ 458 func(SCSI, scsi, 0) \ 459 func(DHCP, dhcp, na) 460#include <config_distro_bootcmd.h> 461 462#define SD_BOOTCOMMAND \ 463 "env exists mcinitcmd && env exists secureboot "\ 464 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ 465 "&& esbc_validate $load_addr; " \ 466 "env exists mcinitcmd && run mcinitcmd " \ 467 "&& mmc read 0x80d00000 0x6800 0x800 " \ 468 "&& fsl_mc lazyapply dpl 0x80d00000; " \ 469 "run distro_bootcmd;run sd_bootcmd; " \ 470 "env exists secureboot && esbc_halt;" 471 472#define IFC_NOR_BOOTCOMMAND \ 473 "env exists mcinitcmd && env exists secureboot "\ 474 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ 475 "&& fsl_mc lazyapply dpl 0x580d00000;" \ 476 "run distro_bootcmd;run nor_bootcmd; " \ 477 "env exists secureboot && esbc_halt;" 478#endif 479 480#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) 481#define CONFIG_FSL_MEMAC 482#define CONFIG_PHYLIB_10G 483#define CONFIG_PHY_VITESSE 484#define CONFIG_PHY_REALTEK 485#define CONFIG_PHY_TERANETICS 486#define SGMII_CARD_PORT1_PHY_ADDR 0x1C 487#define SGMII_CARD_PORT2_PHY_ADDR 0x1d 488#define SGMII_CARD_PORT3_PHY_ADDR 0x1E 489#define SGMII_CARD_PORT4_PHY_ADDR 0x1F 490 491#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 492#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 493#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 494#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 495#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 496#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 497#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 498#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 499#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 500#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 501#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 502#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 503#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 504#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 505#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 506#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 507 508#define CONFIG_ETHPRIME "DPMAC1@xgmii" 509 510#endif 511 512#include <asm/fsl_secure_boot.h> 513 514#endif /* __LS2_QDS_H */ 515