1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2010-2012 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7#ifndef _TEGRA20_COMMON_H_ 8#define _TEGRA20_COMMON_H_ 9#include "tegra-common.h" 10 11/* 12 * NS16550 Configuration 13 */ 14#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ 15 16/* 17 * Miscellaneous configurable options 18 */ 19#define CONFIG_STACKBASE 0x03800000 /* 56MB */ 20 21/*----------------------------------------------------------------------- 22 * Physical Memory Map 23 */ 24 25/* 26 * Memory layout for where various images get loaded by boot scripts: 27 * 28 * scriptaddr can be pretty much anywhere that doesn't conflict with something 29 * else. Put it above BOOTMAPSZ to eliminate conflicts. 30 * 31 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 32 * something else. Put it above BOOTMAPSZ to eliminate conflicts. 33 * 34 * kernel_addr_r must be within the first 128M of RAM in order for the 35 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 36 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 37 * should not overlap that area, or the kernel will have to copy itself 38 * somewhere else before decompression. Similarly, the address of any other 39 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 40 * this up to 32M allows for a sizable kernel to be decompressed below the 41 * compressed load address. 42 * 43 * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for 44 * the compressed kernel to be up to 32M too. 45 * 46 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows 47 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 48 */ 49#define CONFIG_LOADADDR 0x01000000 50#define MEM_LAYOUT_ENV_SETTINGS \ 51 "scriptaddr=0x10000000\0" \ 52 "pxefile_addr_r=0x10100000\0" \ 53 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 54 "fdt_addr_r=0x03000000\0" \ 55 "ramdisk_addr_r=0x03100000\0" 56 57/* Defines for SPL */ 58#define CONFIG_SYS_SPL_MALLOC_START 0x00090000 59#define CONFIG_SPL_STACK 0x000ffffc 60 61/* Align LCD to 1MB boundary */ 62#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE 63 64#ifdef CONFIG_TEGRA_LP0 65#define TEGRA_LP0_ADDR 0x1C406000 66#define TEGRA_LP0_SIZE 0x2000 67#define TEGRA_LP0_VEC \ 68 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ 69 "@" __stringify(TEGRA_LP0_ADDR) " " 70#else 71#define TEGRA_LP0_VEC 72#endif 73 74/* 75 * This parameter affects a TXFILLTUNING field that controls how much data is 76 * sent to the latency fifo before it is sent to the wire. Without this 77 * parameter, the default (2) causes occasional Data Buffer Errors in OUT 78 * packets depending on the buffer address and size. 79 */ 80#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 81#define CONFIG_EHCI_IS_TDI 82 83#define CONFIG_SYS_NAND_SELF_INIT 84#define CONFIG_SYS_NAND_ONFI_DETECTION 85 86#endif /* _TEGRA20_COMMON_H_ */ 87