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8#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
9#define _ASM_ARCH_IMX8MM_CLOCK_H
10
11#ifndef __ASSEMBLY__
12#include <linux/bitops.h>
13#endif
14
15#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
16 { \
17 .rate = (_rate), \
18 .mdiv = (_m), \
19 .pdiv = (_p), \
20 .sdiv = (_s), \
21 .kdiv = (_k), \
22 }
23
24#define LOCK_STATUS BIT(31)
25#define LOCK_SEL_MASK BIT(29)
26#define CLKE_MASK BIT(13)
27#define RST_MASK BIT(9)
28#define BYPASS_MASK BIT(4)
29#define MDIV_SHIFT 12
30#define MDIV_MASK GENMASK(21, 12)
31#define PDIV_SHIFT 4
32#define PDIV_MASK GENMASK(9, 4)
33#define SDIV_SHIFT 0
34#define SDIV_MASK GENMASK(2, 0)
35#define KDIV_SHIFT 0
36#define KDIV_MASK GENMASK(15, 0)
37
38struct imx_int_pll_rate_table {
39 u32 rate;
40 int mdiv;
41 int pdiv;
42 int sdiv;
43 int kdiv;
44};
45
46enum pll_clocks {
47 ANATOP_ARM_PLL,
48 ANATOP_VPU_PLL,
49 ANATOP_GPU_PLL,
50 ANATOP_SYSTEM_PLL1,
51 ANATOP_SYSTEM_PLL2,
52 ANATOP_SYSTEM_PLL3,
53 ANATOP_AUDIO_PLL1,
54 ANATOP_AUDIO_PLL2,
55 ANATOP_VIDEO_PLL,
56 ANATOP_DRAM_PLL,
57};
58
59#ifdef CONFIG_IMX8MP
60enum clk_root_index {
61 ARM_A53_CLK_ROOT = 0,
62 ARM_M7_CLK_ROOT = 1,
63 ML_CLK_ROOT = 2,
64 GPU3D_CORE_CLK_ROOT = 3,
65 GPU3D_SHADER_CLK_ROOT = 4,
66 GPU2D_CLK_ROOT = 5,
67 AUDIO_AXI_CLK_ROOT = 6,
68 HSIO_AXI_CLK_ROOT = 7,
69 MEDIA_ISP_CLK_ROOT = 8,
70 MAIN_AXI_CLK_ROOT = 16,
71 ENET_AXI_CLK_ROOT = 17,
72 NAND_USDHC_BUS_CLK_ROOT = 18,
73 VPU_BUS_CLK_ROOT = 19,
74 MEDIA_AXI_CLK_ROOT = 20,
75 MEDIA_APB_CLK_ROOT = 21,
76 HDMI_APB_CLK_ROOT = 22,
77 HDMI_AXI_CLK_ROOT = 23,
78 GPU_AXI_CLK_ROOT = 24,
79 GPU_AHB_CLK_ROOT = 25,
80 NOC_CLK_ROOT = 26,
81 NOC_IO_CLK_ROOT = 27,
82 ML_AXI_CLK_ROOT = 28,
83 ML_AHB_CLK_ROOT = 29,
84 AHB_CLK_ROOT = 32,
85 IPG_CLK_ROOT = 33,
86 AUDIO_AHB_CLK_ROOT = 34,
87 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
88 MEDIA_DISP2_CLK_ROOT = 38,
89 DRAM_SEL_CFG = 48,
90 CORE_SEL_CFG = 49,
91 DRAM_ALT_CLK_ROOT = 64,
92 DRAM_APB_CLK_ROOT = 65,
93 VPU_G1_CLK_ROOT = 66,
94 VPU_G2_CLK_ROOT = 67,
95 CAN1_CLK_ROOT = 68,
96 CAN2_CLK_ROOT = 69,
97 PCIE_PHY_CLK_ROOT = 71,
98 PCIE_AUX_CLK_ROOT = 72,
99 I2C5_CLK_ROOT = 73,
100 I2C6_CLK_ROOT = 74,
101 SAI1_CLK_ROOT = 75,
102 SAI2_CLK_ROOT = 76,
103 SAI3_CLK_ROOT = 77,
104 SAI4_CLK_ROOT = 78,
105 SAI5_CLK_ROOT = 79,
106 SAI6_CLK_ROOT = 80,
107 ENET_QOS_CLK_ROOT = 81,
108 ENET_QOS_TIMER_CLK_ROOT = 82,
109 ENET_REF_CLK_ROOT = 83,
110 ENET_TIMER_CLK_ROOT = 84,
111 ENET_PHY_REF_CLK_ROOT = 85,
112 NAND_CLK_ROOT = 86,
113 QSPI_CLK_ROOT = 87,
114 USDHC1_CLK_ROOT = 88,
115 USDHC2_CLK_ROOT = 89,
116 I2C1_CLK_ROOT = 90,
117 I2C2_CLK_ROOT = 91,
118 I2C3_CLK_ROOT = 92,
119 I2C4_CLK_ROOT = 93,
120 UART1_CLK_ROOT = 94,
121 UART2_CLK_ROOT = 95,
122 UART3_CLK_ROOT = 96,
123 UART4_CLK_ROOT = 97,
124 USB_CORE_REF_CLK_ROOT = 98,
125 USB_PHY_REF_CLK_ROOT = 99,
126 GIC_CLK_ROOT = 100,
127 ECSPI1_CLK_ROOT = 101,
128 ECSPI2_CLK_ROOT = 102,
129 PWM1_CLK_ROOT = 103,
130 PWM2_CLK_ROOT = 104,
131 PWM3_CLK_ROOT = 105,
132 PWM4_CLK_ROOT = 106,
133 GPT1_CLK_ROOT = 107,
134 GPT2_CLK_ROOT = 108,
135 GPT3_CLK_ROOT = 109,
136 GPT4_CLK_ROOT = 110,
137 GPT5_CLK_ROOT = 111,
138 GPT6_CLK_ROOT = 112,
139 TRACE_CLK_ROOT = 113,
140 WDOG_CLK_ROOT = 114,
141 WRCLK_CLK_ROOT = 115,
142 IPP_DO_CLKO1 = 116,
143 IPP_DO_CLKO2 = 117,
144 HDMI_FDCC_TST_CLK_ROOT = 118,
145 HDMI_27M_CLK_ROOT = 119,
146 HDMI_REF_266M_CLK_ROOT = 120,
147 USDHC3_CLK_ROOT = 121,
148 MEDIA_CAM1_PIX_CLK_ROOT = 122,
149 MEDIA_MIPI_PHY1_REF_CLK_ROOT = 123,
150 MEDIA_DISP1_PIX_CLK_ROOT = 124,
151 MEDIA_CAM2_PIX_CLK_ROOT = 125,
152 MEDIA_LDB_CLK_ROOT = 126,
153 MEMREPAIR_CLK_ROOT = 127,
154 MEDIA_MIPI_TEST_BYTE_CLK = 130,
155 ECSPI3_CLK_ROOT = 131,
156 PDM_CLK_ROOT = 132,
157 VPU_VC8000E_CLK_ROOT = 133,
158 SAI7_CLK_ROOT = 134,
159 CLK_ROOT_MAX,
160};
161#elif defined(CONFIG_IMX8MN)
162enum clk_root_index {
163 ARM_A53_CLK_ROOT = 0,
164 ARM_M7_CLK_ROOT = 1,
165 GPU_CORE_CLK_ROOT = 3,
166 GPU_SHADER_CLK_ROOT = 4,
167 MAIN_AXI_CLK_ROOT = 16,
168 ENET_AXI_CLK_ROOT = 17,
169 NAND_USDHC_BUS_CLK_ROOT = 18,
170 DISPLAY_AXI_CLK_ROOT = 20,
171 DISPLAY_APB_CLK_ROOT = 21,
172 USB_BUS_CLK_ROOT = 23,
173 GPU_AXI_CLK_ROOT = 24,
174 GPU_AHB_CLK_ROOT = 25,
175 NOC_CLK_ROOT = 26,
176 AHB_CLK_ROOT = 32,
177 IPG_CLK_ROOT = 33,
178 AUDIO_AHB_CLK_ROOT = 34,
179 DRAM_SEL_CFG = 48,
180 CORE_SEL_CFG = 49,
181 DRAM_ALT_CLK_ROOT = 64,
182 DRAM_APB_CLK_ROOT = 65,
183 DISPLAY_PIXEL_CLK_ROOT = 74,
184 SAI2_CLK_ROOT = 76,
185 SAI3_CLK_ROOT = 77,
186 SAI5_CLK_ROOT = 79,
187 SAI6_CLK_ROOT = 80,
188 SPDIF1_CLK_ROOT = 81,
189 ENET_REF_CLK_ROOT = 83,
190 ENET_TIMER_CLK_ROOT = 84,
191 ENET_PHY_REF_CLK_ROOT = 85,
192 NAND_CLK_ROOT = 86,
193 QSPI_CLK_ROOT = 87,
194 USDHC1_CLK_ROOT = 88,
195 USDHC2_CLK_ROOT = 89,
196 I2C1_CLK_ROOT = 90,
197 I2C2_CLK_ROOT = 91,
198 I2C3_CLK_ROOT = 92,
199 I2C4_CLK_ROOT = 93,
200 UART1_CLK_ROOT = 94,
201 UART2_CLK_ROOT = 95,
202 UART3_CLK_ROOT = 96,
203 UART4_CLK_ROOT = 97,
204 USB_CORE_REF_CLK_ROOT = 98,
205 USB_PHY_REF_CLK_ROOT = 99,
206 GIC_CLK_ROOT = 100,
207 ECSPI1_CLK_ROOT = 101,
208 ECSPI2_CLK_ROOT = 102,
209 PWM1_CLK_ROOT = 103,
210 PWM2_CLK_ROOT = 104,
211 PWM3_CLK_ROOT = 105,
212 PWM4_CLK_ROOT = 106,
213 GPT1_CLK_ROOT = 107,
214 GPT2_CLK_ROOT = 108,
215 GPT3_CLK_ROOT = 109,
216 GPT4_CLK_ROOT = 110,
217 GPT5_CLK_ROOT = 111,
218 GPT6_CLK_ROOT = 112,
219 TRACE_CLK_ROOT = 113,
220 WDOG_CLK_ROOT = 114,
221 WRCLK_CLK_ROOT = 115,
222 IPP_DO_CLKO1 = 116,
223 IPP_DO_CLKO2 = 117,
224 MIPI_DSI_CORE_CLK_ROOT = 118,
225 DISPLAY_DSI_PHY_REF_CLK_ROOT = 119,
226 MIPI_DSI_DBI_CLK_ROOT = 120,
227 USDHC3_CLK_ROOT = 121,
228 DISPLAY_CAMERA_PIXEL_CLK_ROOT = 122,
229 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
230 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
231 MIPI_CSI2_ESC_CLK_ROOT = 127,
232 ECSPI3_CLK_ROOT = 131,
233 PDM_CLK_ROOT = 132,
234 SAI7_CLK_ROOT = 134,
235 CLK_ROOT_MAX,
236};
237#else
238enum clk_root_index {
239 ARM_A53_CLK_ROOT = 0,
240 ARM_M4_CLK_ROOT = 1,
241 VPU_A53_CLK_ROOT = 2,
242 GPU3D_CLK_ROOT = 3,
243 GPU2D_CLK_ROOT = 4,
244 MAIN_AXI_CLK_ROOT = 16,
245 ENET_AXI_CLK_ROOT = 17,
246 NAND_USDHC_BUS_CLK_ROOT = 18,
247 VPU_BUS_CLK_ROOT = 19,
248 DISPLAY_AXI_CLK_ROOT = 20,
249 DISPLAY_APB_CLK_ROOT = 21,
250 DISPLAY_RTRM_CLK_ROOT = 22,
251 USB_BUS_CLK_ROOT = 23,
252 GPU_AXI_CLK_ROOT = 24,
253 GPU_AHB_CLK_ROOT = 25,
254 NOC_CLK_ROOT = 26,
255 NOC_APB_CLK_ROOT = 27,
256 AHB_CLK_ROOT = 32,
257 IPG_CLK_ROOT = 33,
258 AUDIO_AHB_CLK_ROOT = 34,
259 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
260 DRAM_SEL_CFG = 48,
261 CORE_SEL_CFG = 49,
262 DRAM_ALT_CLK_ROOT = 64,
263 DRAM_APB_CLK_ROOT = 65,
264 VPU_G1_CLK_ROOT = 66,
265 VPU_G2_CLK_ROOT = 67,
266 DISPLAY_DTRC_CLK_ROOT = 68,
267 DISPLAY_DC8000_CLK_ROOT = 69,
268 PCIE_CTRL_CLK_ROOT = 70,
269 PCIE_PHY_CLK_ROOT = 71,
270 PCIE_AUX_CLK_ROOT = 72,
271 DC_PIXEL_CLK_ROOT = 73,
272 LCDIF_PIXEL_CLK_ROOT = 74,
273 SAI1_CLK_ROOT = 75,
274 SAI2_CLK_ROOT = 76,
275 SAI3_CLK_ROOT = 77,
276 SAI4_CLK_ROOT = 78,
277 SAI5_CLK_ROOT = 79,
278 SAI6_CLK_ROOT = 80,
279 SPDIF1_CLK_ROOT = 81,
280 SPDIF2_CLK_ROOT = 82,
281 ENET_REF_CLK_ROOT = 83,
282 ENET_TIMER_CLK_ROOT = 84,
283 ENET_PHY_REF_CLK_ROOT = 85,
284 NAND_CLK_ROOT = 86,
285 QSPI_CLK_ROOT = 87,
286 USDHC1_CLK_ROOT = 88,
287 USDHC2_CLK_ROOT = 89,
288 I2C1_CLK_ROOT = 90,
289 I2C2_CLK_ROOT = 91,
290 I2C3_CLK_ROOT = 92,
291 I2C4_CLK_ROOT = 93,
292 UART1_CLK_ROOT = 94,
293 UART2_CLK_ROOT = 95,
294 UART3_CLK_ROOT = 96,
295 UART4_CLK_ROOT = 97,
296 USB_CORE_REF_CLK_ROOT = 98,
297 USB_PHY_REF_CLK_ROOT = 99,
298 GIC_CLK_ROOT = 100,
299 ECSPI1_CLK_ROOT = 101,
300 ECSPI2_CLK_ROOT = 102,
301 PWM1_CLK_ROOT = 103,
302 PWM2_CLK_ROOT = 104,
303 PWM3_CLK_ROOT = 105,
304 PWM4_CLK_ROOT = 106,
305 GPT1_CLK_ROOT = 107,
306 GPT2_CLK_ROOT = 108,
307 GPT3_CLK_ROOT = 109,
308 GPT4_CLK_ROOT = 110,
309 GPT5_CLK_ROOT = 111,
310 GPT6_CLK_ROOT = 112,
311 TRACE_CLK_ROOT = 113,
312 WDOG_CLK_ROOT = 114,
313 WRCLK_CLK_ROOT = 115,
314 IPP_DO_CLKO1 = 116,
315 IPP_DO_CLKO2 = 117,
316 MIPI_DSI_CORE_CLK_ROOT = 118,
317 MIPI_DSI_PHY_REF_CLK_ROOT = 119,
318 MIPI_DSI_DBI_CLK_ROOT = 120,
319 USDHC3_CLK_ROOT = 121,
320 MIPI_CSI1_CORE_CLK_ROOT = 122,
321 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
322 MIPI_CSI1_ESC_CLK_ROOT = 124,
323 MIPI_CSI2_CORE_CLK_ROOT = 125,
324 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
325 MIPI_CSI2_ESC_CLK_ROOT = 127,
326 PCIE2_CTRL_CLK_ROOT = 128,
327 PCIE2_PHY_CLK_ROOT = 129,
328 PCIE2_AUX_CLK_ROOT = 130,
329 ECSPI3_CLK_ROOT = 131,
330 PDM_CLK_ROOT = 132,
331 VPU_H1_CLK_ROOT = 133,
332 CLK_ROOT_MAX,
333};
334#endif
335
336enum clk_root_src {
337 OSC_24M_CLK,
338 ARM_PLL_CLK,
339 DRAM_PLL1_CLK,
340 VIDEO_PLL2_CLK,
341 VPU_PLL_CLK,
342 GPU_PLL_CLK,
343 SYSTEM_PLL1_800M_CLK,
344 SYSTEM_PLL1_400M_CLK,
345 SYSTEM_PLL1_266M_CLK,
346 SYSTEM_PLL1_200M_CLK,
347 SYSTEM_PLL1_160M_CLK,
348 SYSTEM_PLL1_133M_CLK,
349 SYSTEM_PLL1_100M_CLK,
350 SYSTEM_PLL1_80M_CLK,
351 SYSTEM_PLL1_40M_CLK,
352 SYSTEM_PLL2_1000M_CLK,
353 SYSTEM_PLL2_500M_CLK,
354 SYSTEM_PLL2_333M_CLK,
355 SYSTEM_PLL2_250M_CLK,
356 SYSTEM_PLL2_200M_CLK,
357 SYSTEM_PLL2_166M_CLK,
358 SYSTEM_PLL2_125M_CLK,
359 SYSTEM_PLL2_100M_CLK,
360 SYSTEM_PLL2_50M_CLK,
361 SYSTEM_PLL3_CLK,
362 AUDIO_PLL1_CLK,
363 AUDIO_PLL2_CLK,
364 VIDEO_PLL_CLK,
365 OSC_32K_CLK,
366 EXT_CLK_1,
367 EXT_CLK_2,
368 EXT_CLK_3,
369 EXT_CLK_4,
370 OSC_HDMI_CLK,
371 ARM_A53_ALT_CLK,
372};
373
374enum clk_ccgr_index {
375 CCGR_DVFS = 0,
376 CCGR_ANAMIX = 1,
377 CCGR_CPU = 2,
378 CCGR_CSU = 3,
379 CCGR_DEBUG = 4,
380 CCGR_DDR1 = 5,
381 CCGR_ECSPI1 = 7,
382 CCGR_ECSPI2 = 8,
383 CCGR_ECSPI3 = 9,
384 CCGR_ENET1 = 10,
385 CCGR_GPIO1 = 11,
386 CCGR_GPIO2 = 12,
387 CCGR_GPIO3 = 13,
388 CCGR_GPIO4 = 14,
389 CCGR_GPIO5 = 15,
390 CCGR_GPT1 = 16,
391 CCGR_GPT2 = 17,
392 CCGR_GPT3 = 18,
393 CCGR_GPT4 = 19,
394 CCGR_AAM_8MP = 20,
395 CCGR_GPT5 = 20,
396 CCGR_GPT6 = 21,
397 CCGR_HS = 22,
398 CCGR_I2C1 = 23,
399 CCGR_I2C2 = 24,
400 CCGR_I2C3 = 25,
401 CCGR_I2C4 = 26,
402 CCGR_IOMUX = 27,
403 CCGR_IOMUX1 = 28,
404 CCGR_IOMUX2 = 29,
405 CCGR_IOMUX3 = 30,
406 CCGR_IOMUX4 = 31,
407 CCGR_SNVSMIX_IPG_CLK = 32,
408 CCGR_MU = 33,
409 CCGR_OCOTP = 34,
410 CCGR_OCRAM = 35,
411 CCGR_OCRAM_S = 36,
412 CCGR_PCIE = 37,
413 CCGR_PERFMON1 = 38,
414 CCGR_PERFMON2 = 39,
415 CCGR_PWM1 = 40,
416 CCGR_PWM2 = 41,
417 CCGR_PWM3 = 42,
418 CCGR_PWM4 = 43,
419 CCGR_QOS = 44,
420 CCGR_QOS_DISPMIX = 45,
421 CCGR_QOS_ETHENET = 46,
422 CCGR_QSPI = 47,
423 CCGR_RAWNAND = 48,
424 CCGR_RDC = 49,
425 CCGR_ROM = 50,
426 CCGR_I2C5_8MP = 51,
427 CCGR_SAI1 = 51,
428 CCGR_I2C6_8MP = 52,
429 CCGR_SAI2 = 52,
430 CCGR_SAI3 = 53,
431 CCGR_SAI4 = 54,
432 CCGR_SAI5 = 55,
433 CCGR_SAI6 = 56,
434 CCGR_SCTR = 57,
435 CCGR_SDMA1 = 58,
436 CCGR_SDMA2 = 59,
437 CCGR_SEC_DEBUG = 60,
438 CCGR_SEMA1 = 61,
439 CCGR_SEMA2 = 62,
440 CCGR_IRQ_STEER_8MP = 63,
441 CCGR_SIM_DISPLAY = 63,
442 CCGR_SIM_ENET = 64,
443 CCGR_SIM_M = 65,
444 CCGR_SIM_MAIN = 66,
445 CCGR_SIM_S = 67,
446 CCGR_SIM_WAKEUP = 68,
447 CCGR_GPU2D_8MP = 69,
448 CCGR_SIM_HSIO = 69,
449 CCGR_GPU3D_8MP = 70,
450 CCGR_SIM_VPU = 70,
451 CCGR_SNVS = 71,
452 CCGR_TRACE = 72,
453 CCGR_UART1 = 73,
454 CCGR_UART2 = 74,
455 CCGR_UART3 = 75,
456 CCGR_UART4 = 76,
457 CCGR_USB_MSCALE_PL301 = 77,
458 CCGR_USB_PHY_8MP = 79,
459 CCGR_GPU3D = 79,
460 CCGR_USDHC1 = 81,
461 CCGR_USDHC2 = 82,
462 CCGR_WDOG1 = 83,
463 CCGR_WDOG2 = 84,
464 CCGR_WDOG3 = 85,
465 CCGR_VPUG1 = 86,
466 CCGR_GPU_BUS = 87,
467 CCGR_VPUH1 = 89,
468 CCGR_VPUG2 = 90,
469 CCGR_PDM = 91,
470 CCGR_GIC = 92,
471 CCGR_DISPMIX = 93,
472 CCGR_USDHC3 = 94,
473 CCGR_SDMA3 = 95,
474 CCGR_XTAL = 96,
475 CCGR_PLL = 97,
476 CCGR_TEMP_SENSOR = 98,
477 CCGR_VPUMIX_BUS = 99,
478 CCGR_SAI7 = 101,
479 CCGR_GPU2D = 102,
480 CCGR_MAX
481};
482
483enum clk_src_index {
484 CLK_SRC_CKIL_SYNC_REQ = 0,
485 CLK_SRC_ARM_PLL_EN = 1,
486 CLK_SRC_GPU_PLL_EN = 2,
487 CLK_SRC_VPU_PLL_EN = 3,
488 CLK_SRC_DRAM_PLL_EN = 4,
489 CLK_SRC_SYSTEM_PLL1_EN = 5,
490 CLK_SRC_SYSTEM_PLL2_EN = 6,
491 CLK_SRC_SYSTEM_PLL3_EN = 7,
492 CLK_SRC_AUDIO_PLL1_EN = 8,
493 CLK_SRC_AUDIO_PLL2_EN = 9,
494 CLK_SRC_VIDEO_PLL1_EN = 10,
495 CLK_SRC_RESERVED = 11,
496 CLK_SRC_ARM_PLL = 12,
497 CLK_SRC_GPU_PLL = 13,
498 CLK_SRC_VPU_PLL = 14,
499 CLK_SRC_DRAM_PLL = 15,
500 CLK_SRC_SYSTEM_PLL1_800M = 16,
501 CLK_SRC_SYSTEM_PLL1_400M = 17,
502 CLK_SRC_SYSTEM_PLL1_266M = 18,
503 CLK_SRC_SYSTEM_PLL1_200M = 19,
504 CLK_SRC_SYSTEM_PLL1_160M = 20,
505 CLK_SRC_SYSTEM_PLL1_133M = 21,
506 CLK_SRC_SYSTEM_PLL1_100M = 22,
507 CLK_SRC_SYSTEM_PLL1_80M = 23,
508 CLK_SRC_SYSTEM_PLL1_40M = 24,
509 CLK_SRC_SYSTEM_PLL2_1000M = 25,
510 CLK_SRC_SYSTEM_PLL2_500M = 26,
511 CLK_SRC_SYSTEM_PLL2_333M = 27,
512 CLK_SRC_SYSTEM_PLL2_250M = 28,
513 CLK_SRC_SYSTEM_PLL2_200M = 29,
514 CLK_SRC_SYSTEM_PLL2_166M = 30,
515 CLK_SRC_SYSTEM_PLL2_125M = 31,
516 CLK_SRC_SYSTEM_PLL2_100M = 32,
517 CLK_SRC_SYSTEM_PLL2_50M = 33,
518 CLK_SRC_SYSTEM_PLL3 = 34,
519 CLK_SRC_AUDIO_PLL1 = 35,
520 CLK_SRC_AUDIO_PLL2 = 36,
521 CLK_SRC_VIDEO_PLL1 = 37,
522};
523
524#define INTPLL_LOCK_MASK BIT(31)
525#define INTPLL_LOCK_SEL_MASK BIT(29)
526#define INTPLL_EXT_BYPASS_MASK BIT(28)
527#define INTPLL_DIV20_CLKE_MASK BIT(27)
528#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
529#define INTPLL_DIV10_CLKE_MASK BIT(25)
530#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
531#define INTPLL_DIV8_CLKE_MASK BIT(23)
532#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
533#define INTPLL_DIV6_CLKE_MASK BIT(21)
534#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
535#define INTPLL_DIV5_CLKE_MASK BIT(19)
536#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
537#define INTPLL_DIV4_CLKE_MASK BIT(17)
538#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
539#define INTPLL_DIV3_CLKE_MASK BIT(15)
540#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
541#define INTPLL_DIV2_CLKE_MASK BIT(13)
542#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
543#define INTPLL_CLKE_MASK BIT(11)
544#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
545#define INTPLL_RST_MASK BIT(9)
546#define INTPLL_RST_OVERRIDE_MASK BIT(8)
547#define INTPLL_BYPASS_MASK BIT(4)
548#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
549#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
550
551#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
552#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
553#define INTPLL_MAIN_DIV_SHIFT 12
554#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
555#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
556#define INTPLL_PRE_DIV_SHIFT 4
557#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
558#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
559#define INTPLL_POST_DIV_SHIFT 0
560
561#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
562#define INTPLL_LOCK_CON_DLY_SHIFT 4
563#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
564#define INTPLL_LOCK_CON_OUT_SHIFT 2
565#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
566#define INTPLL_LOCK_CON_IN_SHIFT 0
567
568#define INTPLL_LRD_EN_MASK BIT(21)
569#define INTPLL_FOUT_MASK BIT(20)
570#define INTPLL_AFC_SEL_MASK BIT(19)
571#define INTPLL_PBIAS_CTRL_MASK BIT(18)
572#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
573#define INTPLL_AFCINIT_SEL_MASK BIT(16)
574#define INTPLL_FSEL_MASK BIT(14)
575#define INTPLL_FEED_EN_MASK BIT(13)
576#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
577#define INTPLL_AFC_EN_MASK BIT(2)
578#define INTPLL_ICP_MASK GENMASK(1, 0)
579
580#endif
581
