1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2018 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7#ifndef __G12A_H__ 8#define __G12A_H__ 9 10#ifndef __ASSEMBLY__ 11#include <linux/bitops.h> 12#endif 13 14#define G12A_AOBUS_BASE 0xff800000 15#define G12A_PERIPHS_BASE 0xff634400 16#define G12A_HIU_BASE 0xff63c000 17#define G12A_ETH_PHY_BASE 0xff64c000 18#define G12A_ETH_BASE 0xff3f0000 19 20/* Always-On Peripherals registers */ 21#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2)) 22 23#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90) 24#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93) 25#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94) 26#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95) 27 28#define G12A_AO_BOOT_DEVICE 0xF 29#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000 30#define G12A_AO_MEM_SIZE_SHIFT 16 31#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 32#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16 33#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF 34 35/* Peripherals registers */ 36#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2)) 37 38#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50) 39#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51) 40 41#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0) 42#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2) 43#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) 44#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) 45#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10) 46#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11) 47#define G12A_ETH_REG_0_CLK_EN BIT(12) 48 49#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2)) 50#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11) 51#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12) 52#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13) 53#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14) 54#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15) 55#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16) 56#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17) 57#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18) 58#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20) 59#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21) 60#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22) 61 62/* HIU registers */ 63#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2)) 64 65#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40) 66 67/* Ethernet memory power domain */ 68#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) 69 70#endif /* __G12A_H__ */ 71