LXR uboot/arch/arm/include/asm/arch-mx25/imx-regs.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2009, DENX Software Engineering
   4 * Author: John Rigby <jcrigby@gmail.com
   5 *
   6 *   Based on arch-mx31/imx-regs.h
   7 *      Copyright (C) 2009 Ilya Yanok,
   8 *              Emcraft Systems <yanok@emcraft.com>
   9 *   and arch-mx27/imx-regs.h
  10 *      Copyright (C) 2007 Pengutronix,
  11 *              Sascha Hauer <s.hauer@pengutronix.de>
  12 *      Copyright (C) 2009 Ilya Yanok,
  13 *              Emcraft Systems <yanok@emcraft.com>
  14 */
  15
  16#ifndef _IMX_REGS_H
  17#define _IMX_REGS_H
  18
  19#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  20#include <asm/types.h>
  21
  22/* Clock Control Module (CCM) registers */
  23struct ccm_regs {
  24        u32 mpctl;      /* Core PLL Control */
  25        u32 upctl;      /* USB PLL Control */
  26        u32 cctl;       /* Clock Control */
  27        u32 cgr0;       /* Clock Gating Control 0 */
  28        u32 cgr1;       /* Clock Gating Control 1 */
  29        u32 cgr2;       /* Clock Gating Control 2 */
  30        u32 pcdr[4];    /* PER Clock Dividers */
  31        u32 rcsr;       /* CCM Status */
  32        u32 crdr;       /* CCM Reset and Debug */
  33        u32 dcvr0;      /* DPTC Comparator Value 0 */
  34        u32 dcvr1;      /* DPTC Comparator Value 1 */
  35        u32 dcvr2;      /* DPTC Comparator Value 2 */
  36        u32 dcvr3;      /* DPTC Comparator Value 3 */
  37        u32 ltr0;       /* Load Tracking 0 */
  38        u32 ltr1;       /* Load Tracking 1 */
  39        u32 ltr2;       /* Load Tracking 2 */
  40        u32 ltr3;       /* Load Tracking 3 */
  41        u32 ltbr0;      /* Load Tracking Buffer 0 */
  42        u32 ltbr1;      /* Load Tracking Buffer 1 */
  43        u32 pcmr0;      /* Power Management Control 0 */
  44        u32 pcmr1;      /* Power Management Control 1 */
  45        u32 pcmr2;      /* Power Management Control 2 */
  46        u32 mcr;        /* Miscellaneous Control */
  47        u32 lpimr0;     /* Low Power Interrupt Mask 0 */
  48        u32 lpimr1;     /* Low Power Interrupt Mask 1 */
  49};
  50
  51/* Enhanced SDRAM Controller (ESDRAMC) registers */
  52struct esdramc_regs {
  53        u32 ctl0;       /* control 0 */
  54        u32 cfg0;       /* configuration 0 */
  55        u32 ctl1;       /* control 1 */
  56        u32 cfg1;       /* configuration 1 */
  57        u32 misc;       /* miscellaneous */
  58        u32 pad[3];
  59        u32 cdly1;      /* Delay Line 1 configuration debug */
  60        u32 cdly2;      /* delay line 2 configuration debug */
  61        u32 cdly3;      /* delay line 3 configuration debug */
  62        u32 cdly4;      /* delay line 4 configuration debug */
  63        u32 cdly5;      /* delay line 5 configuration debug */
  64        u32 cdlyl;      /* delay line cycle length debug */
  65};
  66
  67/* General Purpose Timer (GPT) registers */
  68struct gpt_regs {
  69        u32 ctrl;       /* control */
  70        u32 pre;        /* prescaler */
  71        u32 stat;       /* status */
  72        u32 intr;       /* interrupt */
  73        u32 cmp[3];     /* output compare 1-3 */
  74        u32 capt[2];    /* input capture 1-2 */
  75        u32 counter;    /* counter */
  76};
  77
  78/* Watchdog Timer (WDOG) registers */
  79struct wdog_regs {
  80        u16 wcr;        /* Control */
  81        u16 wsr;        /* Service */
  82        u16 wrsr;       /* Reset Status */
  83        u16 wicr;       /* Interrupt Control */
  84        u16 wmcr;       /* Misc Control */
  85};
  86
  87/* IIM control registers */
  88struct iim_regs {
  89        u32 iim_stat;
  90        u32 iim_statm;
  91        u32 iim_err;
  92        u32 iim_emask;
  93        u32 iim_fctl;
  94        u32 iim_ua;
  95        u32 iim_la;
  96        u32 iim_sdat;
  97        u32 iim_prev;
  98        u32 iim_srev;
  99        u32 iim_prg_p;
 100        u32 iim_scs0;
 101        u32 iim_scs1;
 102        u32 iim_scs2;
 103        u32 iim_scs3;
 104        u32 res1[0x1f1];
 105        struct fuse_bank {
 106                u32 fuse_regs[0x20];
 107                u32 fuse_rsvd[0xe0];
 108        } bank[3];
 109};
 110
 111struct fuse_bank0_regs {
 112        u32 fuse0_7[8];
 113        u32 uid[8];
 114        u32 fuse16_25[0xa];
 115        u32 mac_addr[6];
 116};
 117
 118struct fuse_bank1_regs {
 119        u32 fuse0_21[0x16];
 120        u32 usr5;
 121        u32 fuse23_29[7];
 122        u32 usr6[2];
 123};
 124
 125/* Multi-Layer AHB Crossbar Switch (MAX) registers */
 126struct max_regs {
 127        u32 mpr0;
 128        u32 pad00[3];
 129        u32 sgpcr0;
 130        u32 pad01[59];
 131        u32 mpr1;
 132        u32 pad02[3];
 133        u32 sgpcr1;
 134        u32 pad03[59];
 135        u32 mpr2;
 136        u32 pad04[3];
 137        u32 sgpcr2;
 138        u32 pad05[59];
 139        u32 mpr3;
 140        u32 pad06[3];
 141        u32 sgpcr3;
 142        u32 pad07[59];
 143        u32 mpr4;
 144        u32 pad08[3];
 145        u32 sgpcr4;
 146        u32 pad09[251];
 147        u32 mgpcr0;
 148        u32 pad10[63];
 149        u32 mgpcr1;
 150        u32 pad11[63];
 151        u32 mgpcr2;
 152        u32 pad12[63];
 153        u32 mgpcr3;
 154        u32 pad13[63];
 155        u32 mgpcr4;
 156};
 157
 158/* AHB <-> IP-Bus Interface (AIPS) */
 159struct aips_regs {
 160        u32 mpr_0_7;
 161        u32 mpr_8_15;
 162};
 163/* LCD controller registers */
 164struct lcdc_regs {
 165        u32 lssar;      /* Screen Start Address */
 166        u32 lsr;        /* Size */
 167        u32 lvpwr;      /* Virtual Page Width */
 168        u32 lcpr;       /* Cursor Position */
 169        u32 lcwhb;      /* Cursor Width Height and Blink */
 170        u32 lccmr;      /* Color Cursor Mapping */
 171        u32 lpcr;       /* Panel Configuration */
 172        u32 lhcr;       /* Horizontal Configuration */
 173        u32 lvcr;       /* Vertical Configuration */
 174        u32 lpor;       /* Panning Offset */
 175        u32 lscr;       /* Sharp Configuration */
 176        u32 lpccr;      /* PWM Contrast Control */
 177        u32 ldcr;       /* DMA Control */
 178        u32 lrmcr;      /* Refresh Mode Control */
 179        u32 licr;       /* Interrupt Configuration */
 180        u32 lier;       /* Interrupt Enable */
 181        u32 lisr;       /* Interrupt Status */
 182        u32 res0[3];
 183        u32 lgwsar;     /* Graphic Window Start Address */
 184        u32 lgwsr;      /* Graphic Window Size */
 185        u32 lgwvpwr;    /* Graphic Window Virtual Page Width Regist */
 186        u32 lgwpor;     /* Graphic Window Panning Offset */
 187        u32 lgwpr;      /* Graphic Window Position */
 188        u32 lgwcr;      /* Graphic Window Control */
 189        u32 lgwdcr;     /* Graphic Window DMA Control */
 190        u32 res1[5];
 191        u32 lauscr;     /* AUS Mode Control */
 192        u32 lausccr;    /* AUS mode Cursor Control */
 193        u32 res2[31 + 64*7];
 194        u32 bglut;      /* Background Lookup Table */
 195        u32 gwlut;      /* Graphic Window Lookup Table */
 196};
 197
 198/* Wireless External Interface Module Registers */
 199struct weim_regs {
 200        u32 cscr0u;     /* Chip Select 0 Upper Register */
 201        u32 cscr0l;     /* Chip Select 0 Lower Register */
 202        u32 cscr0a;     /* Chip Select 0 Addition Register */
 203        u32 pad0;
 204        u32 cscr1u;     /* Chip Select 1 Upper Register */
 205        u32 cscr1l;     /* Chip Select 1 Lower Register */
 206        u32 cscr1a;     /* Chip Select 1 Addition Register */
 207        u32 pad1;
 208        u32 cscr2u;     /* Chip Select 2 Upper Register */
 209        u32 cscr2l;     /* Chip Select 2 Lower Register */
 210        u32 cscr2a;     /* Chip Select 2 Addition Register */
 211        u32 pad2;
 212        u32 cscr3u;     /* Chip Select 3 Upper Register */
 213        u32 cscr3l;     /* Chip Select 3 Lower Register */
 214        u32 cscr3a;     /* Chip Select 3 Addition Register */
 215        u32 pad3;
 216        u32 cscr4u;     /* Chip Select 4 Upper Register */
 217        u32 cscr4l;     /* Chip Select 4 Lower Register */
 218        u32 cscr4a;     /* Chip Select 4 Addition Register */
 219        u32 pad4;
 220        u32 cscr5u;     /* Chip Select 5 Upper Register */
 221        u32 cscr5l;     /* Chip Select 5 Lower Register */
 222        u32 cscr5a;     /* Chip Select 5 Addition Register */
 223        u32 pad5;
 224        u32 wcr;        /* WEIM Configuration Register */
 225};
 226
 227/* Multi-Master Memory Interface */
 228struct m3if_regs {
 229        u32 ctl;        /* Control Register */
 230        u32 wcfg0;      /* Watermark Configuration Register 0 */
 231        u32 wcfg1;      /* Watermark Configuration Register1 */
 232        u32 wcfg2;      /* Watermark Configuration Register2 */
 233        u32 wcfg3;      /* Watermark Configuration Register 3 */
 234        u32 wcfg4;      /* Watermark Configuration Register 4 */
 235        u32 wcfg5;      /* Watermark Configuration Register 5 */
 236        u32 wcfg6;      /* Watermark Configuration Register 6 */
 237        u32 wcfg7;      /* Watermark Configuration Register 7 */
 238        u32 wcsr;       /* Watermark Control and Status Register */
 239        u32 scfg0;      /* Snooping Configuration Register 0 */
 240        u32 scfg1;      /* Snooping Configuration Register 1 */
 241        u32 scfg2;      /* Snooping Configuration Register 2 */
 242        u32 ssr0;       /* Snooping Status Register 0 */
 243        u32 ssr1;       /* Snooping Status Register 1 */
 244        u32 res0;
 245        u32 mlwe0;      /* Master Lock WEIM CS0 Register */
 246        u32 mlwe1;      /* Master Lock WEIM CS1 Register */
 247        u32 mlwe2;      /* Master Lock WEIM CS2 Register */
 248        u32 mlwe3;      /* Master Lock WEIM CS3 Register */
 249        u32 mlwe4;      /* Master Lock WEIM CS4 Register */
 250        u32 mlwe5;      /* Master Lock WEIM CS5 Register */
 251};
 252
 253/* Pulse width modulation */
 254struct pwm_regs {
 255        u32 cr; /* Control Register */
 256        u32 sr; /* Status Register */
 257        u32 ir; /* Interrupt Register */
 258        u32 sar;        /* Sample Register */
 259        u32 pr; /* Period Register */
 260        u32 cnr;        /* Counter Register */
 261};
 262
 263/* Enhanced Periodic Interrupt Timer */
 264struct epit_regs {
 265        u32 cr; /* Control register */
 266        u32 sr; /* Status register */
 267        u32 lr; /* Load register */
 268        u32 cmpr;       /* Compare register */
 269        u32 cnr;        /* Counter register */
 270};
 271
 272/* CSPI registers */
 273struct cspi_regs {
 274        u32 rxdata;
 275        u32 txdata;
 276        u32 ctrl;
 277        u32 intr;
 278        u32 dma;
 279        u32 stat;
 280        u32 period;
 281        u32 test;
 282};
 283
 284#endif
 285
 286#define ARCH_MXC
 287
 288/* AIPS 1 */
 289#define IMX_AIPS1_BASE          (0x43F00000)
 290#define IMX_MAX_BASE            (0x43F04000)
 291#define IMX_CLKCTL_BASE         (0x43F08000)
 292#define IMX_ETB_SLOT4_BASE      (0x43F0C000)
 293#define IMX_ETB_SLOT5_BASE      (0x43F10000)
 294#define IMX_ECT_CTIO_BASE       (0x43F18000)
 295#define I2C1_BASE_ADDR          (0x43F80000)
 296#define I2C3_BASE_ADDR          (0x43F84000)
 297#define IMX_CAN1_BASE           (0x43F88000)
 298#define IMX_CAN2_BASE           (0x43F8C000)
 299#define UART1_BASE              (0x43F90000)
 300#define UART2_BASE              (0x43F94000)
 301#define I2C2_BASE_ADDR          (0x43F98000)
 302#define IMX_OWIRE_BASE          (0x43F9C000)
 303#define IMX_CSPI1_BASE          (0x43FA4000)
 304#define IMX_KPP_BASE            (0x43FA8000)
 305#define IMX_IOPADMUX_BASE       (0x43FAC000)
 306#define IOMUXC_BASE_ADDR        IMX_IOPADMUX_BASE
 307#define IMX_IOPADCTL_BASE       (0x43FAC22C)
 308#define IMX_IOPADGRPCTL_BASE    (0x43FAC418)
 309#define IMX_IOPADINPUTSEL_BASE  (0x43FAC460)
 310#define IMX_AUDMUX_BASE         (0x43FB0000)
 311#define IMX_ECT_IP1_BASE        (0x43FB8000)
 312#define IMX_ECT_IP2_BASE        (0x43FBC000)
 313
 314/* SPBA */
 315#define IMX_SPBA_BASE           (0x50000000)
 316#define IMX_CSPI3_BASE          (0x50004000)
 317#define UART4_BASE              (0x50008000)
 318#define UART3_BASE              (0x5000C000)
 319#define IMX_CSPI2_BASE          (0x50010000)
 320#define IMX_SSI2_BASE           (0x50014000)
 321#define IMX_ESAI_BASE           (0x50018000)
 322#define IMX_ATA_DMA_BASE        (0x50020000)
 323#define IMX_SIM1_BASE           (0x50024000)
 324#define IMX_SIM2_BASE           (0x50028000)
 325#define UART5_BASE              (0x5002C000)
 326#define IMX_TSC_BASE            (0x50030000)
 327#define IMX_SSI1_BASE           (0x50034000)
 328#define IMX_FEC_BASE            (0x50038000)
 329#define IMX_SPBA_CTRL_BASE      (0x5003C000)
 330
 331/* AIPS 2 */
 332#define IMX_AIPS2_BASE          (0x53F00000)
 333#define IMX_CCM_BASE            (0x53F80000)
 334#define IMX_GPT4_BASE           (0x53F84000)
 335#define IMX_GPT3_BASE           (0x53F88000)
 336#define IMX_GPT2_BASE           (0x53F8C000)
 337#define IMX_GPT1_BASE           (0x53F90000)
 338#define IMX_EPIT1_BASE          (0x53F94000)
 339#define IMX_EPIT2_BASE          (0x53F98000)
 340#define IMX_GPIO4_BASE          (0x53F9C000)
 341#define IMX_PWM2_BASE           (0x53FA0000)
 342#define IMX_GPIO3_BASE          (0x53FA4000)
 343#define IMX_PWM3_BASE           (0x53FA8000)
 344#define IMX_SCC_BASE            (0x53FAC000)
 345#define IMX_SCM_BASE            (0x53FAE000)
 346#define IMX_SMN_BASE            (0x53FAF000)
 347#define IMX_RNGD_BASE           (0x53FB0000)
 348#define IMX_MMC_SDHC1_BASE      (0x53FB4000)
 349#define IMX_MMC_SDHC2_BASE      (0x53FB8000)
 350#define IMX_LCDC_BASE           (0x53FBC000)
 351#define IMX_SLCDC_BASE          (0x53FC0000)
 352#define IMX_PWM4_BASE           (0x53FC8000)
 353#define IMX_GPIO1_BASE          (0x53FCC000)
 354#define IMX_GPIO2_BASE          (0x53FD0000)
 355#define IMX_SDMA_BASE           (0x53FD4000)
 356#define IMX_WDT_BASE            (0x53FDC000)
 357#define WDOG1_BASE_ADDR IMX_WDT_BASE
 358#define IMX_PWM1_BASE           (0x53FE0000)
 359#define IMX_RTIC_BASE           (0x53FEC000)
 360#define IMX_IIM_BASE            (0x53FF0000)
 361#define IIM_BASE_ADDR           IMX_IIM_BASE
 362#define IMX_USB_BASE            (0x53FF4000)
 363/*
 364 * This is in contradiction to the imx25 reference manual, which says that
 365 * port 1's registers start at 0x53FF4200. The correct base address for
 366 * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well.
 367 */
 368#define IMX_USB_PORT_OFFSET     0x400
 369#define IMX_CSI_BASE            (0x53FF8000)
 370#define IMX_DRYICE_BASE         (0x53FFC000)
 371
 372#define IMX_ARM926_ROMPATCH     (0x60000000)
 373#define IMX_ARM926_ASIC         (0x68000000)
 374
 375/* 128K Internal Static RAM */
 376#define IMX_RAM_BASE            (0x78000000)
 377#define IMX_RAM_SIZE            (128 * 1024)
 378
 379/* SDRAM BANKS */
 380#define IMX_SDRAM_BANK0_BASE    (0x80000000)
 381#define IMX_SDRAM_BANK1_BASE    (0x90000000)
 382
 383#define IMX_WEIM_CS0            (0xA0000000)
 384#define IMX_WEIM_CS1            (0xA8000000)
 385#define IMX_WEIM_CS2            (0xB0000000)
 386#define IMX_WEIM_CS3            (0xB2000000)
 387#define IMX_WEIM_CS4            (0xB4000000)
 388#define IMX_ESDRAMC_BASE        (0xB8001000)
 389#define IMX_WEIM_CTRL_BASE      (0xB8002000)
 390#define IMX_M3IF_CTRL_BASE      (0xB8003000)
 391#define IMX_EMI_CTRL_BASE       (0xB8004000)
 392
 393/* NAND Flash Controller */
 394#define IMX_NFC_BASE            (0xBB000000)
 395#define NFC_BASE_ADDR           IMX_NFC_BASE
 396
 397/* CCM bitfields */
 398#define CCM_PLL_MFI_SHIFT       10
 399#define CCM_PLL_MFI_MASK        0xf
 400#define CCM_PLL_MFN_SHIFT       0
 401#define CCM_PLL_MFN_MASK        0x3ff
 402#define CCM_PLL_MFD_SHIFT       16
 403#define CCM_PLL_MFD_MASK        0x3ff
 404#define CCM_PLL_PD_SHIFT        26
 405#define CCM_PLL_PD_MASK         0xf
 406#define CCM_CCTL_ARM_DIV_SHIFT  30
 407#define CCM_CCTL_ARM_DIV_MASK   3
 408#define CCM_CCTL_AHB_DIV_SHIFT  28
 409#define CCM_CCTL_AHB_DIV_MASK   3
 410#define CCM_CCTL_ARM_SRC        (1 << 14)
 411#define CCM_CGR1_GPT1           (1 << 19)
 412#define CCM_PERCLK_REG(clk)     (clk / 4)
 413#define CCM_PERCLK_SHIFT(clk)   (8 * (clk % 4))
 414#define CCM_PERCLK_MASK         0x3f
 415#define CCM_RCSR_NF_16BIT_SEL   (1 << 14)
 416#define CCM_RCSR_NF_PS(v)       ((v >> 26) & 3)
 417#define CCM_CRDR_BT_UART_SRC_SHIFT      29
 418#define CCM_CRDR_BT_UART_SRC_MASK       7
 419
 420/* ESDRAM Controller register bitfields */
 421#define ESDCTL_PRCT(x)          (((x) & 0x3f) << 0)
 422#define ESDCTL_BL               (1 << 7)
 423#define ESDCTL_FP               (1 << 8)
 424#define ESDCTL_PWDT(x)          (((x) & 3) << 10)
 425#define ESDCTL_SREFR(x)         (((x) & 7) << 13)
 426#define ESDCTL_DSIZ_16_UPPER    (0 << 16)
 427#define ESDCTL_DSIZ_16_LOWER    (1 << 16)
 428#define ESDCTL_DSIZ_32          (2 << 16)
 429#define ESDCTL_COL8             (0 << 20)
 430#define ESDCTL_COL9             (1 << 20)
 431#define ESDCTL_COL10            (2 << 20)
 432#define ESDCTL_ROW11            (0 << 24)
 433#define ESDCTL_ROW12            (1 << 24)
 434#define ESDCTL_ROW13            (2 << 24)
 435#define ESDCTL_ROW14            (3 << 24)
 436#define ESDCTL_ROW15            (4 << 24)
 437#define ESDCTL_SP               (1 << 27)
 438#define ESDCTL_SMODE_NORMAL     (0 << 28)
 439#define ESDCTL_SMODE_PRECHARGE  (1 << 28)
 440#define ESDCTL_SMODE_AUTO_REF   (2 << 28)
 441#define ESDCTL_SMODE_LOAD_MODE  (3 << 28)
 442#define ESDCTL_SMODE_MAN_REF    (4 << 28)
 443#define ESDCTL_SDE              (1 << 31)
 444
 445#define ESDCFG_TRC(x)           (((x) & 0xf) << 0)
 446#define ESDCFG_TRCD(x)          (((x) & 0x7) << 4)
 447#define ESDCFG_TCAS(x)          (((x) & 0x3) << 8)
 448#define ESDCFG_TRRD(x)          (((x) & 0x3) << 10)
 449#define ESDCFG_TRAS(x)          (((x) & 0x7) << 12)
 450#define ESDCFG_TWR              (1 << 15)
 451#define ESDCFG_TMRD(x)          (((x) & 0x3) << 16)
 452#define ESDCFG_TRP(x)           (((x) & 0x3) << 18)
 453#define ESDCFG_TWTR             (1 << 20)
 454#define ESDCFG_TXP(x)           (((x) & 0x3) << 21)
 455
 456#define ESDMISC_RST             (1 << 1)
 457#define ESDMISC_MDDREN          (1 << 2)
 458#define ESDMISC_MDDR_DL_RST     (1 << 3)
 459#define ESDMISC_MDDR_MDIS       (1 << 4)
 460#define ESDMISC_LHD             (1 << 5)
 461#define ESDMISC_MA10_SHARE      (1 << 6)
 462#define ESDMISC_SDRAM_RDY       (1 << 31)
 463
 464/* GPT bits */
 465#define GPT_CTRL_SWR            (1 << 15)       /* Software reset */
 466#define GPT_CTRL_FRR            (1 << 9)        /* Freerun / restart */
 467#define GPT_CTRL_CLKSOURCE_32   (4 << 6)        /* Clock source */
 468#define GPT_CTRL_TEN            1               /* Timer enable */
 469
 470/* WDOG enable */
 471#define WCR_WDE                 0x04
 472#define WSR_UNLOCK1             0x5555
 473#define WSR_UNLOCK2             0xAAAA
 474
 475/* MAX bits */
 476#define MAX_MGPCR_AULB(x)       (((x) & 0x7) << 0)
 477
 478/* M3IF bits */
 479#define M3IF_CTL_MRRP(x)        (((x) & 0xff) << 0)
 480
 481/* WEIM bits */
 482/* 13 fields of the upper CS control register */
 483#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
 484                cnc, wsc, ew, wws, edc) \
 485                ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
 486                (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
 487                (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
 488/* 12 fields of the lower CS control register */
 489#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
 490                csa, ebc, dsz, csn, psr, cre, wrap, csen) \
 491                ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
 492                (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
 493                (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
 494/* 14 fields of the additional CS control register */
 495#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
 496                wwu, age, cnc2, fce) \
 497                ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
 498                (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
 499                (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
 500                (age) << 2 | (cnc2) << 1 | (fce) << 0)
 501
 502/* Names used in GPIO driver */
 503#define GPIO1_BASE_ADDR         IMX_GPIO1_BASE
 504#define GPIO2_BASE_ADDR         IMX_GPIO2_BASE
 505#define GPIO3_BASE_ADDR         IMX_GPIO3_BASE
 506#define GPIO4_BASE_ADDR         IMX_GPIO4_BASE
 507
 508/*
 509 * CSPI register definitions
 510 */
 511#define MXC_CSPI
 512#define MXC_CSPICTRL_EN         (1 << 0)
 513#define MXC_CSPICTRL_MODE       (1 << 1)
 514#define MXC_CSPICTRL_XCH        (1 << 2)
 515#define MXC_CSPICTRL_SMC        (1 << 3)
 516#define MXC_CSPICTRL_POL        (1 << 4)
 517#define MXC_CSPICTRL_PHA        (1 << 5)
 518#define MXC_CSPICTRL_SSCTL      (1 << 6)
 519#define MXC_CSPICTRL_SSPOL      (1 << 7)
 520#define MXC_CSPICTRL_CHIPSELECT(x)      (((x) & 0x3) << 12)
 521#define MXC_CSPICTRL_BITCOUNT(x)        (((x) & 0xfff) << 20)
 522#define MXC_CSPICTRL_DATARATE(x)        (((x) & 0x7) << 16)
 523#define MXC_CSPICTRL_TC         (1 << 7)
 524#define MXC_CSPICTRL_RXOVF      (1 << 6)
 525#define MXC_CSPICTRL_MAXBITS    0xfff
 526#define MXC_CSPIPERIOD_32KHZ    (1 << 15)
 527#define MAX_SPI_BYTES   4
 528
 529#define MXC_SPI_BASE_ADDRESSES \
 530        IMX_CSPI1_BASE, \
 531        IMX_CSPI2_BASE, \
 532        IMX_CSPI3_BASE
 533
 534#endif                          /* _IMX_REGS_H */
 535