1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> 4 * (C) Copyright 2007-2013 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * Jerry Wang <wangflord@allwinnertech.com> 7 */ 8 9#ifndef _SUNXI_CPU_SUN9I_H 10#define _SUNXI_CPU_SUN9I_H 11 12#define REGS_AHB0_BASE 0x01C00000 13#define REGS_AHB1_BASE 0x00800000 14#define REGS_AHB2_BASE 0x03000000 15#define REGS_APB0_BASE 0x06000000 16#define REGS_APB1_BASE 0x07000000 17#define REGS_RCPUS_BASE 0x08000000 18 19#define SUNXI_SRAM_D_BASE 0x08100000 20 21/* AHB0 Module */ 22#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) 23#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) 24 25#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000) 26/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */ 27#define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200) 28 29#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000) 30#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000) 31#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000) 32#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000) 33#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000) 34 35#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000) 36#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000) 37#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000) 38#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000) 39 40#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000) 41#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) 42#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) 43 44#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) 45#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) 46#define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000) 47#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) 48#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000) 49 50/* AHB1 Module */ 51#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) 52#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) 53#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) 54#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000) 55#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000) 56 57/* AHB2 Module */ 58#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000) 59#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000) 60#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000) 61#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000) 62#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000) 63 64#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000) 65#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000) 66#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000) 67 68#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000) 69#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000) 70#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000) 71#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000) 72 73#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000) 74#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000) 75#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000) 76#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000) 77/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */ 78#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100) 79#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000) 80 81/* APB0 Module */ 82#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) 83#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) 84#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800) 85#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) 86#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) 87#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) 88 89/* APB1 Module */ 90#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000) 91#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400) 92#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800) 93#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00) 94#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000) 95#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400) 96#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) 97#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) 98#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) 99#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400) 100#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800) 101 102/* RCPUS Module */ 103#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) 104#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) 105#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00) 106#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) 107 108/* Misc. */ 109#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ 110#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) 111 112#ifndef __ASSEMBLY__ 113void sunxi_board_init(void); 114void sunxi_reset(void); 115int sunxi_get_sid(unsigned int *sid); 116#endif 117 118#endif /* _SUNXI_CPU_SUN9I_H */ 119