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7#ifndef _TEGRA_PINMUX_H_
8#define _TEGRA_PINMUX_H_
9
10#include <linux/types.h>
11
12#include <asm/arch/tegra.h>
13
14
15enum pmux_pull {
16 PMUX_PULL_NORMAL = 0,
17 PMUX_PULL_DOWN,
18 PMUX_PULL_UP,
19};
20
21
22enum pmux_tristate {
23 PMUX_TRI_NORMAL = 0,
24 PMUX_TRI_TRISTATE = 1,
25};
26
27#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
28enum pmux_pin_io {
29 PMUX_PIN_OUTPUT = 0,
30 PMUX_PIN_INPUT = 1,
31 PMUX_PIN_NONE,
32};
33#endif
34
35#ifdef TEGRA_PMX_PINS_HAVE_LOCK
36enum pmux_pin_lock {
37 PMUX_PIN_LOCK_DEFAULT = 0,
38 PMUX_PIN_LOCK_DISABLE,
39 PMUX_PIN_LOCK_ENABLE,
40};
41#endif
42
43#ifdef TEGRA_PMX_PINS_HAVE_OD
44enum pmux_pin_od {
45 PMUX_PIN_OD_DEFAULT = 0,
46 PMUX_PIN_OD_DISABLE,
47 PMUX_PIN_OD_ENABLE,
48};
49#endif
50
51#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
52enum pmux_pin_ioreset {
53 PMUX_PIN_IO_RESET_DEFAULT = 0,
54 PMUX_PIN_IO_RESET_DISABLE,
55 PMUX_PIN_IO_RESET_ENABLE,
56};
57#endif
58
59#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
60enum pmux_pin_rcv_sel {
61 PMUX_PIN_RCV_SEL_DEFAULT = 0,
62 PMUX_PIN_RCV_SEL_NORMAL,
63 PMUX_PIN_RCV_SEL_HIGH,
64};
65#endif
66
67#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
68enum pmux_pin_e_io_hv {
69 PMUX_PIN_E_IO_HV_DEFAULT = 0,
70 PMUX_PIN_E_IO_HV_NORMAL,
71 PMUX_PIN_E_IO_HV_HIGH,
72};
73#endif
74
75#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
76
77enum pmux_lpmd {
78 PMUX_LPMD_X8 = 0,
79 PMUX_LPMD_X4,
80 PMUX_LPMD_X2,
81 PMUX_LPMD_X,
82 PMUX_LPMD_NONE = -1,
83};
84#endif
85
86#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
87
88enum pmux_schmt {
89 PMUX_SCHMT_DISABLE = 0,
90 PMUX_SCHMT_ENABLE = 1,
91 PMUX_SCHMT_NONE = -1,
92};
93#endif
94
95#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
96
97enum pmux_hsm {
98 PMUX_HSM_DISABLE = 0,
99 PMUX_HSM_ENABLE = 1,
100 PMUX_HSM_NONE = -1,
101};
102#endif
103
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108
109
110struct pmux_pingrp_config {
111 u32 pingrp:16;
112 u32 func:8;
113 u32 pull:2;
114 u32 tristate:2;
115#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
116 u32 io:2;
117#endif
118#ifdef TEGRA_PMX_PINS_HAVE_LOCK
119 u32 lock:2;
120#endif
121#ifdef TEGRA_PMX_PINS_HAVE_OD
122 u32 od:2;
123#endif
124#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
125 u32 ioreset:2;
126#endif
127#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
128 u32 rcv_sel:2;
129
130#endif
131#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
132 u32 e_io_hv:2;
133#endif
134#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
135 u32 schmt:2;
136#endif
137#ifdef TEGRA_PMX_PINS_HAVE_HSM
138 u32 hsm:2;
139#endif
140};
141
142#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
143
144void pinmux_set_tristate_input_clamping(void);
145void pinmux_clear_tristate_input_clamping(void);
146#endif
147
148
149void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
150
151
152void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
153
154
155void pinmux_tristate_enable(enum pmux_pingrp pin);
156
157
158void pinmux_tristate_disable(enum pmux_pingrp pin);
159
160#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
161
162void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
163#endif
164
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170
171void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
172 int len);
173
174struct pmux_pingrp_desc {
175 u8 funcs[4];
176#if defined(CONFIG_TEGRA20)
177 u8 ctl_id;
178 u8 pull_id;
179#endif
180};
181
182extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
183
184#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
185
186#define PMUX_SLWF_MIN 0
187#define PMUX_SLWF_MAX 3
188#define PMUX_SLWF_NONE -1
189
190#define PMUX_SLWR_MIN 0
191#define PMUX_SLWR_MAX 3
192#define PMUX_SLWR_NONE -1
193
194#define PMUX_DRVUP_MIN 0
195#define PMUX_DRVUP_MAX 127
196#define PMUX_DRVUP_NONE -1
197
198#define PMUX_DRVDN_MIN 0
199#define PMUX_DRVDN_MAX 127
200#define PMUX_DRVDN_NONE -1
201
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203
204
205struct pmux_drvgrp_config {
206 u32 drvgrp:16;
207 u32 slwf:3;
208 u32 slwr:3;
209 u32 drvup:8;
210 u32 drvdn:8;
211#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
212 u32 lpmd:3;
213#endif
214#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
215 u32 schmt:2;
216#endif
217#ifdef TEGRA_PMX_GRPS_HAVE_HSM
218 u32 hsm:2;
219#endif
220};
221
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226
227
228void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
229 int len);
230
231#endif
232
233#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
234struct pmux_mipipadctrlgrp_config {
235 u32 grp:16;
236 u32 func:8;
237};
238
239void pinmux_config_mipipadctrlgrp_table(
240 const struct pmux_mipipadctrlgrp_config *config, int len);
241
242struct pmux_mipipadctrlgrp_desc {
243 u8 funcs[2];
244};
245
246extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups;
247#endif
248
249#endif
250