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9#include <common.h>
10#include <clock_legacy.h>
11#include <command.h>
12#include <div64.h>
13#include <log.h>
14#include <asm/io.h>
15#include <linux/errno.h>
16#include <asm/arch/imx-regs.h>
17#include <asm/arch/crm_regs.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/sys_proto.h>
20
21struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
22 ANATOP_BASE_ADDR;
23struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
24
25#ifdef CONFIG_FSL_ESDHC_IMX
26DECLARE_GLOBAL_DATA_PTR;
27#endif
28
29int get_clocks(void)
30{
31#ifdef CONFIG_FSL_ESDHC_IMX
32#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
33 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
34#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
35 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
36#else
37 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
38#endif
39#endif
40 return 0;
41}
42
43u32 get_ahb_clk(void)
44{
45 return get_root_clk(AHB_CLK_ROOT);
46}
47
48static u32 get_ipg_clk(void)
49{
50
51
52
53
54 return get_ahb_clk() / 2;
55}
56
57u32 imx_get_uartclk(void)
58{
59 return get_root_clk(UART_CLK_ROOT);
60}
61
62u32 imx_get_fecclk(void)
63{
64 return get_root_clk(ENET_AXI_CLK_ROOT);
65}
66
67#ifdef CONFIG_MXC_OCOTP
68void enable_ocotp_clk(unsigned char enable)
69{
70 clock_enable(CCGR_OCOTP, enable);
71}
72
73void enable_thermal_clk(void)
74{
75 enable_ocotp_clk(1);
76}
77#endif
78
79void enable_usboh3_clk(unsigned char enable)
80{
81 u32 target;
82
83 if (enable) {
84
85 clock_enable(CCGR_USB_HSIC, 0);
86
87
88 target = CLK_ROOT_ON |
89 USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
90 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
91 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
92 clock_set_target_val(USB_HSIC_CLK_ROOT, target);
93
94
95 clock_enable(CCGR_USB_CTRL, 1);
96 clock_enable(CCGR_USB_HSIC, 1);
97 clock_enable(CCGR_USB_PHY1, 1);
98 clock_enable(CCGR_USB_PHY2, 1);
99 } else {
100 clock_enable(CCGR_USB_CTRL, 0);
101 clock_enable(CCGR_USB_HSIC, 0);
102 clock_enable(CCGR_USB_PHY1, 0);
103 clock_enable(CCGR_USB_PHY2, 0);
104 }
105}
106
107static u32 decode_pll(enum pll_clocks pll, u32 infreq)
108{
109 u32 reg, div_sel;
110 u32 num, denom;
111
112
113
114
115
116 switch (pll) {
117 case PLL_CORE:
118 reg = readl(&ccm_anatop->pll_arm);
119
120 if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
121 return 0;
122
123 if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
124 return MXC_HCLK;
125
126 div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
127 CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
128
129 return (infreq * div_sel) / 2;
130
131 case PLL_SYS:
132 reg = readl(&ccm_anatop->pll_480);
133
134 if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
135 return 0;
136
137 if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
138 return MXC_HCLK;
139
140 if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
141 CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
142 return 480000000u;
143 else
144 return 528000000u;
145
146 case PLL_ENET:
147 reg = readl(&ccm_anatop->pll_enet);
148
149 if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
150 return 0;
151
152 if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
153 return MXC_HCLK;
154
155 return 1000000000u;
156
157 case PLL_DDR:
158 reg = readl(&ccm_anatop->pll_ddr);
159
160 if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
161 return 0;
162
163 num = ccm_anatop->pll_ddr_num;
164 denom = ccm_anatop->pll_ddr_denom;
165
166 if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
167 return MXC_HCLK;
168
169 div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
170 CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
171
172 return infreq * (div_sel + num / denom);
173
174 case PLL_USB:
175 return 480000000u;
176
177 default:
178 printf("Unsupported pll clocks %d\n", pll);
179 break;
180 }
181
182 return 0;
183}
184
185static u32 mxc_get_pll_sys_derive(int derive)
186{
187 u32 freq, div, frac;
188 u32 reg;
189
190 div = 1;
191 reg = readl(&ccm_anatop->pll_480);
192 freq = decode_pll(PLL_SYS, MXC_HCLK);
193
194 switch (derive) {
195 case PLL_SYS_MAIN_480M_CLK:
196 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
197 return 0;
198 else
199 return freq;
200 case PLL_SYS_MAIN_240M_CLK:
201 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
202 return 0;
203 else
204 return freq / 2;
205 case PLL_SYS_MAIN_120M_CLK:
206 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
207 return 0;
208 else
209 return freq / 4;
210 case PLL_SYS_PFD0_392M_CLK:
211 reg = readl(&ccm_anatop->pfd_480a);
212 if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
213 return 0;
214 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
215 CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
216 break;
217 case PLL_SYS_PFD0_196M_CLK:
218 if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
219 return 0;
220 reg = readl(&ccm_anatop->pfd_480a);
221 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
222 CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
223 div = 2;
224 break;
225 case PLL_SYS_PFD1_332M_CLK:
226 reg = readl(&ccm_anatop->pfd_480a);
227 if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
228 return 0;
229 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
230 CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
231 break;
232 case PLL_SYS_PFD1_166M_CLK:
233 if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
234 return 0;
235 reg = readl(&ccm_anatop->pfd_480a);
236 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
237 CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
238 div = 2;
239 break;
240 case PLL_SYS_PFD2_270M_CLK:
241 reg = readl(&ccm_anatop->pfd_480a);
242 if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
243 return 0;
244 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
245 CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
246 break;
247 case PLL_SYS_PFD2_135M_CLK:
248 if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
249 return 0;
250 reg = readl(&ccm_anatop->pfd_480a);
251 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
252 CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
253 div = 2;
254 break;
255 case PLL_SYS_PFD3_CLK:
256 reg = readl(&ccm_anatop->pfd_480a);
257 if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
258 return 0;
259 frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
260 CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
261 break;
262 case PLL_SYS_PFD4_CLK:
263 reg = readl(&ccm_anatop->pfd_480b);
264 if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
265 return 0;
266 frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
267 CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
268 break;
269 case PLL_SYS_PFD5_CLK:
270 reg = readl(&ccm_anatop->pfd_480b);
271 if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
272 return 0;
273 frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
274 CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
275 break;
276 case PLL_SYS_PFD6_CLK:
277 reg = readl(&ccm_anatop->pfd_480b);
278 if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
279 return 0;
280 frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
281 CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
282 break;
283 case PLL_SYS_PFD7_CLK:
284 reg = readl(&ccm_anatop->pfd_480b);
285 if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
286 return 0;
287 frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
288 CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
289 break;
290 default:
291 printf("Error derived pll_sys clock %d\n", derive);
292 return 0;
293 }
294
295 return ((freq / frac) * 18) / div;
296}
297
298static u32 mxc_get_pll_enet_derive(int derive)
299{
300 u32 freq, reg;
301
302 freq = decode_pll(PLL_ENET, MXC_HCLK);
303 reg = readl(&ccm_anatop->pll_enet);
304
305 switch (derive) {
306 case PLL_ENET_MAIN_500M_CLK:
307 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
308 return freq / 2;
309 break;
310 case PLL_ENET_MAIN_250M_CLK:
311 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
312 return freq / 4;
313 break;
314 case PLL_ENET_MAIN_125M_CLK:
315 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
316 return freq / 8;
317 break;
318 case PLL_ENET_MAIN_100M_CLK:
319 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
320 return freq / 10;
321 break;
322 case PLL_ENET_MAIN_50M_CLK:
323 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
324 return freq / 20;
325 break;
326 case PLL_ENET_MAIN_40M_CLK:
327 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
328 return freq / 25;
329 break;
330 case PLL_ENET_MAIN_25M_CLK:
331 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
332 return freq / 40;
333 break;
334 default:
335 printf("Error derived pll_enet clock %d\n", derive);
336 break;
337 }
338
339 return 0;
340}
341
342static u32 mxc_get_pll_ddr_derive(int derive)
343{
344 u32 freq, reg;
345
346 freq = decode_pll(PLL_DDR, MXC_HCLK);
347 reg = readl(&ccm_anatop->pll_ddr);
348
349 switch (derive) {
350 case PLL_DRAM_MAIN_1066M_CLK:
351 return freq;
352 case PLL_DRAM_MAIN_533M_CLK:
353 if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
354 return freq / 2;
355 break;
356 default:
357 printf("Error derived pll_ddr clock %d\n", derive);
358 break;
359 }
360
361 return 0;
362}
363
364static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
365{
366 switch (pll) {
367 case PLL_SYS:
368 return mxc_get_pll_sys_derive(derive);
369 case PLL_ENET:
370 return mxc_get_pll_enet_derive(derive);
371 case PLL_DDR:
372 return mxc_get_pll_ddr_derive(derive);
373 default:
374 printf("Error pll.\n");
375 return 0;
376 }
377}
378
379static u32 get_root_src_clk(enum clk_root_src root_src)
380{
381 switch (root_src) {
382 case OSC_24M_CLK:
383 return 24000000u;
384 case PLL_ARM_MAIN_800M_CLK:
385 return decode_pll(PLL_CORE, MXC_HCLK);
386
387 case PLL_SYS_MAIN_480M_CLK:
388 case PLL_SYS_MAIN_240M_CLK:
389 case PLL_SYS_MAIN_120M_CLK:
390 case PLL_SYS_PFD0_392M_CLK:
391 case PLL_SYS_PFD0_196M_CLK:
392 case PLL_SYS_PFD1_332M_CLK:
393 case PLL_SYS_PFD1_166M_CLK:
394 case PLL_SYS_PFD2_270M_CLK:
395 case PLL_SYS_PFD2_135M_CLK:
396 case PLL_SYS_PFD3_CLK:
397 case PLL_SYS_PFD4_CLK:
398 case PLL_SYS_PFD5_CLK:
399 case PLL_SYS_PFD6_CLK:
400 case PLL_SYS_PFD7_CLK:
401 return mxc_get_pll_derive(PLL_SYS, root_src);
402
403 case PLL_ENET_MAIN_500M_CLK:
404 case PLL_ENET_MAIN_250M_CLK:
405 case PLL_ENET_MAIN_125M_CLK:
406 case PLL_ENET_MAIN_100M_CLK:
407 case PLL_ENET_MAIN_50M_CLK:
408 case PLL_ENET_MAIN_40M_CLK:
409 case PLL_ENET_MAIN_25M_CLK:
410 return mxc_get_pll_derive(PLL_ENET, root_src);
411
412 case PLL_DRAM_MAIN_1066M_CLK:
413 case PLL_DRAM_MAIN_533M_CLK:
414 return mxc_get_pll_derive(PLL_DDR, root_src);
415
416 case PLL_AUDIO_MAIN_CLK:
417 return decode_pll(PLL_AUDIO, MXC_HCLK);
418 case PLL_VIDEO_MAIN_CLK:
419 return decode_pll(PLL_VIDEO, MXC_HCLK);
420
421 case PLL_USB_MAIN_480M_CLK:
422 return decode_pll(PLL_USB, MXC_HCLK);
423
424 case REF_1M_CLK:
425 return 1000000;
426 case OSC_32K_CLK:
427 return MXC_CLK32;
428
429 case EXT_CLK_1:
430 case EXT_CLK_2:
431 case EXT_CLK_3:
432 case EXT_CLK_4:
433 printf("No EXT CLK supported??\n");
434 break;
435 };
436
437 return 0;
438}
439
440u32 get_root_clk(enum clk_root_index clock_id)
441{
442 enum clk_root_src root_src;
443 u32 post_podf, pre_podf, auto_podf, root_src_clk;
444 int auto_en;
445
446 if (clock_root_enabled(clock_id) <= 0)
447 return 0;
448
449 if (clock_get_prediv(clock_id, &pre_podf) < 0)
450 return 0;
451
452 if (clock_get_postdiv(clock_id, &post_podf) < 0)
453 return 0;
454
455 if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
456 return 0;
457
458 if (auto_en == 0)
459 auto_podf = 0;
460
461 if (clock_get_src(clock_id, &root_src) < 0)
462 return 0;
463
464 root_src_clk = get_root_src_clk(root_src);
465
466
467
468
469
470 return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
471 (auto_podf + 1);
472}
473
474static u32 get_ddrc_clk(void)
475{
476 u32 reg, freq;
477 enum root_post_div post_div;
478
479 reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
480 if (reg & CLK_ROOT_MUX_MASK)
481
482 freq = get_root_clk(DRAM_ALT_CLK_ROOT);
483 else
484
485 freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
486
487 post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
488
489 return freq / (post_div + 1) / 2;
490}
491
492unsigned int mxc_get_clock(enum mxc_clock clk)
493{
494 switch (clk) {
495 case MXC_ARM_CLK:
496 return get_root_clk(ARM_A7_CLK_ROOT);
497 case MXC_AXI_CLK:
498 return get_root_clk(MAIN_AXI_CLK_ROOT);
499 case MXC_AHB_CLK:
500 return get_root_clk(AHB_CLK_ROOT);
501 case MXC_IPG_CLK:
502 return get_ipg_clk();
503 case MXC_I2C_CLK:
504 return get_root_clk(I2C1_CLK_ROOT);
505 case MXC_UART_CLK:
506 return get_root_clk(UART1_CLK_ROOT);
507 case MXC_CSPI_CLK:
508 return get_root_clk(ECSPI1_CLK_ROOT);
509 case MXC_DDR_CLK:
510 return get_ddrc_clk();
511 case MXC_ESDHC_CLK:
512 return get_root_clk(USDHC1_CLK_ROOT);
513 case MXC_ESDHC2_CLK:
514 return get_root_clk(USDHC2_CLK_ROOT);
515 case MXC_ESDHC3_CLK:
516 return get_root_clk(USDHC3_CLK_ROOT);
517 default:
518 printf("Unsupported mxc_clock %d\n", clk);
519 break;
520 }
521
522 return 0;
523}
524
525#ifdef CONFIG_SYS_I2C_MXC
526
527int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
528{
529 u32 target;
530
531 if (i2c_num >= 4)
532 return -EINVAL;
533
534 if (enable) {
535 clock_enable(CCGR_I2C1 + i2c_num, 0);
536
537
538
539 target = CLK_ROOT_ON |
540 I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
541 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
542 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
543 clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
544
545 clock_enable(CCGR_I2C1 + i2c_num, 1);
546 } else {
547 clock_enable(CCGR_I2C1 + i2c_num, 0);
548 }
549
550 return 0;
551}
552#endif
553
554static void init_clk_esdhc(void)
555{
556 u32 target;
557
558
559 clock_enable(CCGR_USDHC1, 0);
560 clock_enable(CCGR_USDHC2, 0);
561 clock_enable(CCGR_USDHC3, 0);
562
563
564 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
565 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
566 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
567 clock_set_target_val(USDHC1_CLK_ROOT, target);
568
569 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
570 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
571 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
572 clock_set_target_val(USDHC2_CLK_ROOT, target);
573
574 target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
575 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
576 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
577 clock_set_target_val(USDHC3_CLK_ROOT, target);
578
579
580 clock_enable(CCGR_USDHC1, 1);
581 clock_enable(CCGR_USDHC2, 1);
582 clock_enable(CCGR_USDHC3, 1);
583}
584
585static void init_clk_uart(void)
586{
587 u32 target;
588
589
590 clock_enable(CCGR_UART1, 0);
591 clock_enable(CCGR_UART2, 0);
592 clock_enable(CCGR_UART3, 0);
593 clock_enable(CCGR_UART4, 0);
594 clock_enable(CCGR_UART5, 0);
595 clock_enable(CCGR_UART6, 0);
596 clock_enable(CCGR_UART7, 0);
597
598
599 target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
600 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
601 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
602 clock_set_target_val(UART1_CLK_ROOT, target);
603
604 target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
605 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
606 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
607 clock_set_target_val(UART2_CLK_ROOT, target);
608
609 target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
610 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
611 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
612 clock_set_target_val(UART3_CLK_ROOT, target);
613
614 target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
615 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
616 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
617 clock_set_target_val(UART4_CLK_ROOT, target);
618
619 target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
620 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
621 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
622 clock_set_target_val(UART5_CLK_ROOT, target);
623
624 target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
625 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
626 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
627 clock_set_target_val(UART6_CLK_ROOT, target);
628
629 target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
630 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
631 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
632 clock_set_target_val(UART7_CLK_ROOT, target);
633
634
635 clock_enable(CCGR_UART1, 1);
636 clock_enable(CCGR_UART2, 1);
637 clock_enable(CCGR_UART3, 1);
638 clock_enable(CCGR_UART4, 1);
639 clock_enable(CCGR_UART5, 1);
640 clock_enable(CCGR_UART6, 1);
641 clock_enable(CCGR_UART7, 1);
642}
643
644static void init_clk_weim(void)
645{
646 u32 target;
647
648
649 clock_enable(CCGR_WEIM, 0);
650
651
652 target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
653 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
654 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
655 clock_set_target_val(EIM_CLK_ROOT, target);
656
657
658 clock_enable(CCGR_WEIM, 1);
659}
660
661static void init_clk_ecspi(void)
662{
663 u32 target;
664
665
666 clock_enable(CCGR_ECSPI1, 0);
667 clock_enable(CCGR_ECSPI2, 0);
668 clock_enable(CCGR_ECSPI3, 0);
669 clock_enable(CCGR_ECSPI4, 0);
670
671
672 target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
673 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
674 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
675 clock_set_target_val(ECSPI1_CLK_ROOT, target);
676
677 target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
678 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
679 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
680 clock_set_target_val(ECSPI2_CLK_ROOT, target);
681
682 target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
683 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
684 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
685 clock_set_target_val(ECSPI3_CLK_ROOT, target);
686
687 target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
688 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
689 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
690 clock_set_target_val(ECSPI4_CLK_ROOT, target);
691
692
693 clock_enable(CCGR_ECSPI1, 1);
694 clock_enable(CCGR_ECSPI2, 1);
695 clock_enable(CCGR_ECSPI3, 1);
696 clock_enable(CCGR_ECSPI4, 1);
697}
698
699static void init_clk_wdog(void)
700{
701 u32 target;
702
703
704 clock_enable(CCGR_WDOG1, 0);
705 clock_enable(CCGR_WDOG2, 0);
706 clock_enable(CCGR_WDOG3, 0);
707 clock_enable(CCGR_WDOG4, 0);
708
709
710 target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
711 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
712 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
713 clock_set_target_val(WDOG_CLK_ROOT, target);
714
715
716 clock_enable(CCGR_WDOG1, 1);
717 clock_enable(CCGR_WDOG2, 1);
718 clock_enable(CCGR_WDOG3, 1);
719 clock_enable(CCGR_WDOG4, 1);
720}
721
722#ifdef CONFIG_MXC_EPDC
723static void init_clk_epdc(void)
724{
725 u32 target;
726
727
728 clock_enable(CCGR_EPDC, 0);
729
730
731 target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
732 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
733 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
734 clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
735
736
737 clock_enable(CCGR_EPDC, 1);
738}
739#endif
740
741static int enable_pll_enet(void)
742{
743 u32 reg;
744 s32 timeout = 100000;
745
746 reg = readl(&ccm_anatop->pll_enet);
747
748 if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
749 reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
750 writel(reg, &ccm_anatop->pll_enet);
751
752 while (timeout--) {
753 if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
754 break;
755 }
756
757 if (timeout <= 0) {
758
759 reg |= ANADIG_PLL_ENET_PWDN_MASK;
760 return -ETIME;
761 }
762 }
763
764
765 writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
766
767 writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
768 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
769 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
770 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
771 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
772 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
773 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
774 &ccm_anatop->pll_enet_set);
775
776 return 0;
777}
778static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
779 u32 post_div)
780{
781 u32 reg = 0;
782 ulong start;
783
784 debug("pll5 div = %d, num = %d, denom = %d\n",
785 pll_div, pll_num, pll_denom);
786
787
788 writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
789 CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
790 CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
791 CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
792 CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
793 CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
794 &ccm_anatop->pll_video_clr);
795
796
797 switch (post_div) {
798 case 1:
799 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
800 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
801 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
802 &ccm_anatop->pll_video_set);
803 break;
804 case 2:
805 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
806 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
807 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
808 &ccm_anatop->pll_video_set);
809 break;
810 case 3:
811 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
812 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
813 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
814 &ccm_anatop->pll_video_set);
815 break;
816 case 4:
817 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
818 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
819 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
820 &ccm_anatop->pll_video_set);
821 break;
822 case 0:
823 default:
824 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
825 CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
826 CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
827 &ccm_anatop->pll_video_set);
828 break;
829 }
830
831 writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
832 &ccm_anatop->pll_video_num);
833
834 writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
835 &ccm_anatop->pll_video_denom);
836
837
838 start = get_timer(0);
839
840 do {
841 reg = readl(&ccm_anatop->pll_video);
842 if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
843
844 writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
845 &ccm_anatop->pll_video_set);
846 return 0;
847 }
848 } while (get_timer(0) < (start + 10));
849
850 printf("Lock PLL5 timeout\n");
851
852 return 1;
853}
854
855int set_clk_qspi(void)
856{
857 u32 target;
858
859
860 clock_enable(CCGR_QSPI, 0);
861
862
863 target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
864 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
865 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
866 clock_set_target_val(QSPI_CLK_ROOT, target);
867
868
869 clock_enable(CCGR_QSPI, 1);
870
871 return 0;
872}
873
874int set_clk_nand(void)
875{
876 u32 target;
877
878
879 clock_enable(CCGR_RAWNAND, 0);
880
881 enable_pll_enet();
882
883 target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
884 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
885 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
886 clock_set_target_val(NAND_CLK_ROOT, target);
887
888
889 clock_enable(CCGR_RAWNAND, 1);
890
891 return 0;
892}
893
894void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
895{
896 u32 hck = MXC_HCLK/1000;
897 u32 min = hck * 27;
898 u32 max = hck * 54;
899 u32 temp, best = 0;
900 u32 i, j, pred = 1, postd = 1;
901 u32 pll_div, pll_num, pll_denom, post_div = 0;
902 u32 target;
903
904 debug("mxs_set_lcdclk, freq = %d\n", freq);
905
906 clock_enable(CCGR_LCDIF, 0);
907
908 temp = (freq * 8 * 8);
909 if (temp < min) {
910 for (i = 1; i <= 4; i++) {
911 if ((temp * (1 << i)) > min) {
912 post_div = i;
913 freq = (freq * (1 << i));
914 break;
915 }
916 }
917
918 if (5 == i) {
919 printf("Fail to set rate to %dkhz", freq);
920 return;
921 }
922 }
923
924 for (i = 1; i <= 8; i++) {
925 for (j = 1; j <= 8; j++) {
926 temp = freq * i * j;
927 if (temp > max || temp < min)
928 continue;
929
930 if (best == 0 || temp < best) {
931 best = temp;
932 pred = i;
933 postd = j;
934 }
935 }
936 }
937
938 if (best == 0) {
939 printf("Fail to set rate to %dkhz", freq);
940 return;
941 }
942
943 debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
944
945 pll_div = best / hck;
946 pll_denom = 1000000;
947 pll_num = (best - hck * pll_div) * pll_denom / hck;
948
949 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
950 return;
951
952 target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
953 CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
954 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
955
956 clock_enable(CCGR_LCDIF, 1);
957}
958
959#ifdef CONFIG_FEC_MXC
960int set_clk_enet(enum enet_freq type)
961{
962 u32 target;
963 int ret;
964 u32 enet1_ref, enet2_ref;
965
966
967 clock_enable(CCGR_ENET1, 0);
968 clock_enable(CCGR_ENET2, 0);
969
970 switch (type) {
971 case ENET_125MHZ:
972 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
973 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
974 break;
975 case ENET_50MHZ:
976 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
977 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
978 break;
979 case ENET_25MHZ:
980 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
981 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
982 break;
983 default:
984 return -EINVAL;
985 }
986
987 ret = enable_pll_enet();
988 if (ret != 0)
989 return ret;
990
991
992 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
993 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
994 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
995 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
996
997 target = CLK_ROOT_ON | enet1_ref |
998 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
999 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1000 clock_set_target_val(ENET1_REF_CLK_ROOT, target);
1001
1002 target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
1003 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1004 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
1005 clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
1006
1007 target = CLK_ROOT_ON | enet2_ref |
1008 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1009 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1010 clock_set_target_val(ENET2_REF_CLK_ROOT, target);
1011
1012 target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
1013 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1014 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
1015 clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
1016
1017#ifdef CONFIG_FEC_MXC_25M_REF_CLK
1018 target = CLK_ROOT_ON |
1019 ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
1020 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1021 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1022 clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
1023#endif
1024
1025 clock_enable(CCGR_ENET1, 1);
1026 clock_enable(CCGR_ENET2, 1);
1027
1028 return 0;
1029}
1030#endif
1031
1032
1033void clock_init(void)
1034{
1035
1036
1037
1038
1039
1040
1041
1042 u32 reg;
1043
1044
1045
1046
1047
1048 reg = readl(&ccm_anatop->pfd_480b);
1049
1050 reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
1051 CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
1052 reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
1053
1054 writel(reg, &ccm_anatop->pfd_480b);
1055
1056 init_clk_esdhc();
1057 init_clk_uart();
1058 init_clk_weim();
1059 init_clk_ecspi();
1060 init_clk_wdog();
1061#ifdef CONFIG_MXC_EPDC
1062 init_clk_epdc();
1063#endif
1064
1065 enable_usboh3_clk(1);
1066
1067 clock_enable(CCGR_SNVS, 1);
1068
1069#ifdef CONFIG_NAND_MXS
1070 clock_enable(CCGR_RAWNAND, 1);
1071#endif
1072
1073 if (IS_ENABLED(CONFIG_IMX_RDC)) {
1074 clock_enable(CCGR_RDC, 1);
1075 clock_enable(CCGR_SEMA1, 1);
1076 clock_enable(CCGR_SEMA2, 1);
1077 }
1078}
1079
1080#ifdef CONFIG_IMX_HAB
1081void hab_caam_clock_enable(unsigned char enable)
1082{
1083 if (enable)
1084 clock_enable(CCGR_CAAM, 1);
1085 else
1086 clock_enable(CCGR_CAAM, 0);
1087}
1088#endif
1089
1090#ifdef CONFIG_MXC_EPDC
1091void epdc_clock_enable(void)
1092{
1093 clock_enable(CCGR_EPDC, 1);
1094}
1095void epdc_clock_disable(void)
1096{
1097 clock_enable(CCGR_EPDC, 0);
1098}
1099#endif
1100
1101#ifndef CONFIG_SPL_BUILD
1102
1103
1104
1105int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
1106 char *const argv[])
1107{
1108 u32 freq;
1109 freq = decode_pll(PLL_CORE, MXC_HCLK);
1110 printf("PLL_CORE %8d MHz\n", freq / 1000000);
1111 freq = decode_pll(PLL_SYS, MXC_HCLK);
1112 printf("PLL_SYS %8d MHz\n", freq / 1000000);
1113 freq = decode_pll(PLL_ENET, MXC_HCLK);
1114 printf("PLL_NET %8d MHz\n", freq / 1000000);
1115
1116 printf("\n");
1117
1118 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1119 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1120#ifdef CONFIG_MXC_SPI
1121 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1122#endif
1123 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1124 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1125 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1126 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1127 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1128 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1129
1130 return 0;
1131}
1132
1133U_BOOT_CMD(
1134 clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
1135 "display clocks",
1136 ""
1137);
1138#endif
1139
