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13#include <common.h>
14#include <debug_uart.h>
15#include <fdtdec.h>
16#include <init.h>
17#include <spl.h>
18#include <asm/arch/sys_proto.h>
19#include <linux/sizes.h>
20#include <asm/emif.h>
21#include <asm/omap_common.h>
22#include <linux/compiler.h>
23#include <asm/system.h>
24#include <dm/root.h>
25
26DECLARE_GLOBAL_DATA_PTR;
27
28void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
29{
30 int i;
31 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
32
33 for (i = 0; i < size; i++, pad++)
34 writew(pad->val, base + pad->offset);
35}
36
37static void set_mux_conf_regs(void)
38{
39 switch (omap_hw_init_context()) {
40 case OMAP_INIT_CONTEXT_SPL:
41 set_muxconf_regs();
42 break;
43 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
44 break;
45 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
46 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
47 set_muxconf_regs();
48 break;
49 }
50}
51
52u32 cortex_rev(void)
53{
54
55 unsigned int rev;
56
57
58 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
59
60 return rev;
61}
62
63static void omap_rev_string(void)
64{
65 u32 omap_rev = omap_revision();
66 u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
67 u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
68 u32 major_rev = (omap_rev & 0x00000F00) >> 8;
69 u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
70
71 const char *sec_s, *package = NULL;
72
73 switch (get_device_type()) {
74 case TST_DEVICE:
75 sec_s = "TST";
76 break;
77 case EMU_DEVICE:
78 sec_s = "EMU";
79 break;
80 case HS_DEVICE:
81 sec_s = "HS";
82 break;
83 case GP_DEVICE:
84 sec_s = "GP";
85 break;
86 default:
87 sec_s = "?";
88 }
89
90#if defined(CONFIG_DRA7XX)
91 if (is_dra76x()) {
92 switch (omap_rev & 0xF) {
93 case DRA762_ABZ_PACKAGE:
94 package = "ABZ";
95 break;
96 case DRA762_ACD_PACKAGE:
97 default:
98 package = "ACD";
99 break;
100 }
101 }
102#endif
103
104 if (soc_variant)
105 printf("OMAP");
106 else
107 printf("DRA");
108 printf("%x-%s ES%x.%x", omap_variant, sec_s, major_rev, minor_rev);
109 if (package)
110 printf(" %s package\n", package);
111 else
112 puts("\n");
113}
114
115#ifdef CONFIG_SPL_BUILD
116void spl_display_print(void)
117{
118 omap_rev_string();
119}
120#endif
121
122void __weak srcomp_enable(void)
123{
124}
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131
132void __weak do_board_detect(void)
133{
134}
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141
142void __weak vcores_init(void)
143{
144}
145
146void s_init(void)
147{
148}
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155
156void __weak init_package_revision(void)
157{
158}
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174
175void early_system_init(void)
176{
177#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
178 int ret;
179 int rescan;
180#endif
181 init_omap_revision();
182 hw_data_init();
183 init_package_revision();
184
185#ifdef CONFIG_SPL_BUILD
186 if (warm_reset())
187 force_emif_self_refresh();
188#endif
189 watchdog_init();
190 set_mux_conf_regs();
191#ifdef CONFIG_SPL_BUILD
192 srcomp_enable();
193 do_io_settings();
194#endif
195 setup_early_clocks();
196
197#ifdef CONFIG_SPL_BUILD
198
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202
203 save_omap_boot_params();
204 spl_early_init();
205#endif
206 do_board_detect();
207
208#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
209
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213
214 ret = fdtdec_resetup(&rescan);
215 if (!ret && rescan) {
216 dm_uninit();
217 dm_init_and_scan(true);
218 }
219#endif
220
221 vcores_init();
222#ifdef CONFIG_DEBUG_UART_OMAP
223 debug_uart_init();
224#endif
225 prcm_init();
226}
227
228#ifdef CONFIG_SPL_BUILD
229void board_init_f(ulong dummy)
230{
231 early_system_init();
232#ifdef CONFIG_BOARD_EARLY_INIT_F
233 board_early_init_f();
234#endif
235
236 sdram_init();
237 gd->ram_size = omap_sdram_size();
238}
239#endif
240
241int arch_cpu_init_dm(void)
242{
243 early_system_init();
244 return 0;
245}
246
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250
251void wait_for_command_complete(struct watchdog *wd_base)
252{
253 int pending = 1;
254 do {
255 pending = readl(&wd_base->wwps);
256 } while (pending);
257}
258
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262
263void watchdog_init(void)
264{
265 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
266
267 writel(WD_UNLOCK1, &wd2_base->wspr);
268 wait_for_command_complete(wd2_base);
269 writel(WD_UNLOCK2, &wd2_base->wspr);
270}
271
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279u32 omap_sdram_size(void)
280{
281 u32 section, i, valid;
282 u64 sdram_start = 0, sdram_end = 0, addr,
283 size, total_size = 0, trap_size = 0, trap_start = 0;
284
285 for (i = 0; i < 4; i++) {
286 section = __raw_readl(DMM_BASE + i*4);
287 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
288 (EMIF_SDRC_ADDRSPC_SHIFT);
289 addr = section & EMIF_SYS_ADDR_MASK;
290
291
292 if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
293 (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) {
294 size = ((section & EMIF_SYS_SIZE_MASK) >>
295 EMIF_SYS_SIZE_SHIFT);
296 size = 1 << size;
297 size *= SZ_16M;
298
299 if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
300 if (!sdram_start || (addr < sdram_start))
301 sdram_start = addr;
302 if (!sdram_end || ((addr + size) > sdram_end))
303 sdram_end = addr + size;
304 } else {
305 trap_size = size;
306 trap_start = addr;
307 }
308 }
309 }
310
311 if ((trap_start >= sdram_start) && (trap_start < sdram_end))
312 total_size = (sdram_end - sdram_start) - (trap_size);
313 else
314 total_size = sdram_end - sdram_start;
315
316 return total_size;
317}
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324int dram_init(void)
325{
326 sdram_init();
327 gd->ram_size = omap_sdram_size();
328 return 0;
329}
330
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333
334int checkboard(void)
335{
336 puts(sysinfo.board_string);
337 return 0;
338}
339
340#if defined(CONFIG_DISPLAY_CPUINFO)
341
342
343
344int print_cpuinfo(void)
345{
346 puts("CPU : ");
347 omap_rev_string();
348
349 return 0;
350}
351#endif
352