LXR uboot/arch/arm/mach-socfpga/wrap_pll_config

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4 *
   5 */
   6
   7#include <common.h>
   8#include <asm/arch/clock_manager.h>
   9#include <asm/io.h>
  10#include <asm/arch/handoff_s10.h>
  11#include <asm/arch/system_manager.h>
  12
  13const struct cm_config * const cm_get_default_config(void)
  14{
  15        struct cm_config *cm_handoff_cfg = (struct cm_config *)
  16                (S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
  17        u32 *conversion = (u32 *)cm_handoff_cfg;
  18        u32 i;
  19        u32 handoff_clk = readl(S10_HANDOFF_CLOCK);
  20
  21        if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) {
  22                writel(swab32(handoff_clk), S10_HANDOFF_CLOCK);
  23                for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
  24                        conversion[i] = swab32(conversion[i]);
  25                return cm_handoff_cfg;
  26        } else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
  27                return cm_handoff_cfg;
  28        }
  29
  30        return NULL;
  31}
  32
  33const unsigned int cm_get_osc_clk_hz(void)
  34{
  35#ifdef CONFIG_SPL_BUILD
  36
  37        u32 clock = readl(HANDOFF_CLOCK_OSC);
  38
  39        writel(clock,
  40               socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
  41#endif
  42        return readl(socfpga_get_sysmgr_addr() +
  43                     SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
  44}
  45
  46const unsigned int cm_get_intosc_clk_hz(void)
  47{
  48        return CLKMGR_INTOSC_HZ;
  49}
  50
  51const unsigned int cm_get_fpga_clk_hz(void)
  52{
  53#ifdef CONFIG_SPL_BUILD
  54        u32 clock = readl(HANDOFF_CLOCK_FPGA);
  55
  56        writel(clock,
  57               socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
  58#endif
  59        return readl(socfpga_get_sysmgr_addr() +
  60                     SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
  61}
  62