LXR uboot/arch/mips/mach-mscc/dram.c

   1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2/*
   3 * Copyright (c) 2018 Microsemi Corporation
   4 */
   5
   6#include <common.h>
   7#include <init.h>
   8
   9#include <asm/io.h>
  10#include <asm/types.h>
  11
  12#include <mach/tlb.h>
  13#include <mach/ddr.h>
  14
  15DECLARE_GLOBAL_DATA_PTR;
  16
  17static inline int vcoreiii_train_bytelane(void)
  18{
  19        int ret;
  20
  21        ret = hal_vcoreiii_train_bytelane(0);
  22
  23#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
  24        defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
  25        if (ret)
  26                return ret;
  27        ret = hal_vcoreiii_train_bytelane(1);
  28#endif
  29
  30        return ret;
  31}
  32
  33int vcoreiii_ddr_init(void)
  34{
  35        register int res;
  36
  37        if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
  38              & ICPU_MEMCTRL_STAT_INIT_DONE)) {
  39                hal_vcoreiii_init_memctl();
  40                hal_vcoreiii_wait_memctl();
  41                if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane())
  42                        hal_vcoreiii_ddr_failed();
  43        }
  44
  45        res = dram_check();
  46        if (res == 0)
  47                hal_vcoreiii_ddr_verified();
  48        else
  49                hal_vcoreiii_ddr_failed();
  50
  51        /*  Remap DDR to kuseg: Clear boot-mode */
  52        clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  53                     ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
  54        /* - and read-back to activate/verify */
  55        readl(BASE_CFG + ICPU_GENERAL_CTRL);
  56
  57        return res;
  58}
  59
  60int print_cpuinfo(void)
  61{
  62        printf("MSCC VCore-III MIPS 24Kec\n");
  63
  64        return 0;
  65}
  66
  67int dram_init(void)
  68{
  69        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  70        return 0;
  71}
  72