LXR uboot/arch/riscv/cpu/fu540/cache.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2020 SiFive, Inc
   4 *
   5 * Authors:
   6 *   Pragnesh Patel <pragnesh.patel@sifive.com>
   7 */
   8
   9#include <common.h>
  10#include <asm/io.h>
  11#include <linux/bitops.h>
  12
  13/* Register offsets */
  14#define L2_CACHE_CONFIG 0x000
  15#define L2_CACHE_ENABLE 0x008
  16
  17#define MASK_NUM_WAYS   GENMASK(15, 8)
  18#define NUM_WAYS_SHIFT  8
  19
  20DECLARE_GLOBAL_DATA_PTR;
  21
  22int cache_enable_ways(void)
  23{
  24        const void *blob = gd->fdt_blob;
  25        int node = (-FDT_ERR_NOTFOUND);
  26        fdt_addr_t base;
  27        u32 config;
  28        u32 ways;
  29
  30        volatile u32 *enable;
  31
  32        node = fdt_node_offset_by_compatible(blob, -1,
  33                                             "sifive,fu540-c000-ccache");
  34
  35        if (node < 0)
  36                return node;
  37
  38        base = fdtdec_get_addr(blob, node, "reg");
  39        if (base == FDT_ADDR_T_NONE)
  40                return FDT_ADDR_T_NONE;
  41
  42        config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
  43        ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
  44
  45        enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
  46
  47        /* memory barrier */
  48        mb();
  49        (*enable) = ways - 1;
  50        /* memory barrier */
  51        mb();
  52        return 0;
  53}
  54