LXR uboot/board/Marvell/db-88f6820-gp/db-88f6820-gp.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
   4 */
   5
   6#include <common.h>
   7#include <i2c.h>
   8#include <init.h>
   9#include <miiphy.h>
  10#include <net.h>
  11#include <netdev.h>
  12#include <asm/io.h>
  13#include <asm/arch/cpu.h>
  14#include <asm/arch/soc.h>
  15#include <linux/bitops.h>
  16
  17#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  18#include <../serdes/a38x/high_speed_env_spec.h>
  19
  20DECLARE_GLOBAL_DATA_PTR;
  21
  22/*
  23 * Those values and defines are taken from the Marvell U-Boot version
  24 * "u-boot-2013.01-2014_T3.0"
  25 */
  26#define DB_GP_88F68XX_GPP_OUT_ENA_LOW                                   \
  27        (~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |  \
  28           BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |  \
  29           BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  30#define DB_GP_88F68XX_GPP_OUT_ENA_MID                                   \
  31        (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |       \
  32           BIT(16) | BIT(17) | BIT(18)))
  33
  34#define DB_GP_88F68XX_GPP_OUT_VAL_LOW   0x0
  35#define DB_GP_88F68XX_GPP_OUT_VAL_MID   0x0
  36#define DB_GP_88F68XX_GPP_POL_LOW       0x0
  37#define DB_GP_88F68XX_GPP_POL_MID       0x0
  38
  39/* IO expander on Marvell GP board includes e.g. fan enabling */
  40struct marvell_io_exp {
  41        u8 chip;
  42        u8 addr;
  43        u8 val;
  44};
  45
  46static struct marvell_io_exp io_exp[] = {
  47        { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
  48        { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
  49        { 0x20, 2, 0x1D }, /* Output Data, register#0 */
  50        { 0x20, 3, 0x18 }, /* Output Data, register#1 */
  51        { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits  */
  52        { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits  */
  53        { 0x21, 2, 0x08 }, /* Output Data, register#0 */
  54        { 0x21, 3, 0xC0 }  /* Output Data, register#1 */
  55};
  56
  57static struct serdes_map board_serdes_map[] = {
  58        {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  59        {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  60        {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  61        {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  62        {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  63        {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  64};
  65
  66int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  67{
  68        *serdes_map_array = board_serdes_map;
  69        *count = ARRAY_SIZE(board_serdes_map);
  70        return 0;
  71}
  72
  73/*
  74 * Define the DDR layout / topology here in the board file. This will
  75 * be used by the DDR3 init code in the SPL U-Boot version to configure
  76 * the DDR3 controller.
  77 */
  78static struct mv_ddr_topology_map board_topology_map = {
  79        DEBUG_LEVEL_ERROR,
  80        0x1, /* active interfaces */
  81        /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  82        { { { {0x1, 0, 0, 0},
  83              {0x1, 0, 0, 0},
  84              {0x1, 0, 0, 0},
  85              {0x1, 0, 0, 0},
  86              {0x1, 0, 0, 0} },
  87            SPEED_BIN_DDR_1866L,        /* speed_bin */
  88            MV_DDR_DEV_WIDTH_8BIT,      /* memory_width */
  89            MV_DDR_DIE_CAP_4GBIT,       /* mem_size */
  90            MV_DDR_FREQ_800,            /* frequency */
  91            0, 0,                       /* cas_wl cas_l */
  92            MV_DDR_TEMP_LOW,            /* temperature */
  93            MV_DDR_TIM_DEFAULT} },      /* timing */
  94        BUS_MASK_32BIT,                 /* Busses mask */
  95        MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
  96        { {0} },                        /* raw spd data */
  97        {0}                             /* timing parameters */
  98};
  99
 100struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
 101{
 102        /* Return the board topology as defined in the board code */
 103        return &board_topology_map;
 104}
 105
 106int board_early_init_f(void)
 107{
 108        /* Configure MPP */
 109        writel(0x11111111, MVEBU_MPP_BASE + 0x00);
 110        writel(0x11111111, MVEBU_MPP_BASE + 0x04);
 111        writel(0x11244011, MVEBU_MPP_BASE + 0x08);
 112        writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
 113        writel(0x22200002, MVEBU_MPP_BASE + 0x10);
 114        writel(0x30042022, MVEBU_MPP_BASE + 0x14);
 115        writel(0x55550555, MVEBU_MPP_BASE + 0x18);
 116        writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
 117
 118        /* Set GPP Out value */
 119        writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
 120        writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
 121
 122        /* Set GPP Polarity */
 123        writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
 124        writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
 125
 126        /* Set GPP Out Enable */
 127        writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
 128        writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
 129
 130        return 0;
 131}
 132
 133int board_init(void)
 134{
 135        int i;
 136
 137        /* adress of boot parameters */
 138        gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 139
 140        /* Init I2C IO expanders */
 141        for (i = 0; i < ARRAY_SIZE(io_exp); i++)
 142                i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
 143
 144        return 0;
 145}
 146
 147int checkboard(void)
 148{
 149        puts("Board: Marvell DB-88F6820-GP\n");
 150
 151        return 0;
 152}
 153
 154int board_eth_init(bd_t *bis)
 155{
 156        cpu_eth_init(bis); /* Built in controller(s) come first */
 157        return pci_eth_init(bis);
 158}
 159