LXR uboot/board/armltd/integrator/integrator.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2002
   4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   5 * Marius Groeger <mgroeger@sysgo.de>
   6 *
   7 * (C) Copyright 2002
   8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
   9 *
  10 * (C) Copyright 2003
  11 * Texas Instruments, <www.ti.com>
  12 * Kshitij Gupta <Kshitij@ti.com>
  13 *
  14 * (C) Copyright 2004
  15 * ARM Ltd.
  16 * Philippe Robin, <philippe.robin@arm.com>
  17 */
  18
  19#include <common.h>
  20#include <bootstage.h>
  21#include <cpu_func.h>
  22#include <dm.h>
  23#include <env.h>
  24#include <init.h>
  25#include <net.h>
  26#include <netdev.h>
  27#include <asm/io.h>
  28#include <dm/platform_data/serial_pl01x.h>
  29#include "arm-ebi.h"
  30#include "integrator-sc.h"
  31#include <asm/mach-types.h>
  32
  33DECLARE_GLOBAL_DATA_PTR;
  34
  35static const struct pl01x_serial_platdata serial_platdata = {
  36        .base = 0x16000000,
  37#ifdef CONFIG_ARCH_CINTEGRATOR
  38        .type = TYPE_PL011,
  39        .clock = 14745600,
  40#else
  41        .type = TYPE_PL010,
  42        .clock = 0, /* Not used for PL010 */
  43#endif
  44};
  45
  46U_BOOT_DEVICE(integrator_serials) = {
  47        .name = "serial_pl01x",
  48        .platdata = &serial_platdata,
  49};
  50
  51void peripheral_power_enable (void);
  52
  53#if defined(CONFIG_SHOW_BOOT_PROGRESS)
  54void show_boot_progress(int progress)
  55{
  56        printf("Boot reached stage %d\n", progress);
  57}
  58#endif
  59
  60#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
  61
  62/*
  63 * Miscellaneous platform dependent initialisations
  64 */
  65
  66int board_init (void)
  67{
  68        u32 val;
  69
  70        /* arch number of Integrator Board */
  71#ifdef CONFIG_ARCH_CINTEGRATOR
  72        gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
  73#else
  74        gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
  75#endif
  76
  77        /* adress of boot parameters */
  78        gd->bd->bi_boot_params = 0x00000100;
  79
  80#ifdef CONFIG_CM_REMAP
  81extern void cm_remap(void);
  82        cm_remap();     /* remaps writeable memory to 0x00000000 */
  83#endif
  84
  85#ifdef CONFIG_ARCH_CINTEGRATOR
  86        /*
  87         * Flash protection on the Integrator/CP is in a simple register
  88         */
  89        val = readl(CP_FLASHPROG);
  90        val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
  91        writel(val, CP_FLASHPROG);
  92#else
  93        /*
  94         * The Integrator/AP has some special protection mechanisms
  95         * for the external memories, first the External Bus Interface (EBI)
  96         * then the system controller (SC).
  97         *
  98         * The system comes up with the flash memory non-writable and
  99         * configuration locked. If we want U-Boot to be used for flash
 100         * access we cannot have the flash memory locked.
 101         */
 102        writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
 103        val = readl(EBI_BASE + EBI_CSR1_REG);
 104        val &= EBI_CSR_WREN_MASK;
 105        val |= EBI_CSR_WREN_ENABLE;
 106        writel(val, EBI_BASE + EBI_CSR1_REG);
 107        writel(0, EBI_BASE + EBI_LOCK_REG);
 108
 109        /*
 110         * Set up the system controller to remove write protection from
 111         * the flash memory and enable Vpp
 112         */
 113        writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
 114#endif
 115
 116        icache_enable();
 117
 118        return 0;
 119}
 120
 121int misc_init_r (void)
 122{
 123        env_set("verify", "n");
 124        return (0);
 125}
 126
 127/*
 128 * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
 129 * from there, which means we cannot test the RAM underneath the ROM at this
 130 * point. It will be unmapped later on, when we are executing from the
 131 * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
 132 * RAM on higher addresses works fine.
 133 */
 134#define REMAPPED_FLASH_SZ 0x40000
 135
 136int dram_init (void)
 137{
 138        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 139#ifdef CONFIG_CM_SPD_DETECT
 140        {
 141extern void dram_query(void);
 142        u32 cm_reg_sdram;
 143        u32 sdram_shift;
 144
 145        dram_query();   /* Assembler accesses to CM registers */
 146                        /* Queries the SPD values             */
 147
 148        /* Obtain the SDRAM size from the CM SDRAM register */
 149
 150        cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
 151        /*   Register         SDRAM size
 152         *
 153         *   0xXXXXXXbbb000bb    16 MB
 154         *   0xXXXXXXbbb001bb    32 MB
 155         *   0xXXXXXXbbb010bb    64 MB
 156         *   0xXXXXXXbbb011bb   128 MB
 157         *   0xXXXXXXbbb100bb   256 MB
 158         *
 159         */
 160        sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
 161        gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
 162                                    REMAPPED_FLASH_SZ,
 163                                    0x01000000 << sdram_shift);
 164        }
 165#else
 166        gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
 167                                    REMAPPED_FLASH_SZ,
 168                                    PHYS_SDRAM_1_SIZE);
 169#endif /* CM_SPD_DETECT */
 170        /* We only have one bank of RAM, set it to whatever was detected */
 171        gd->bd->bi_dram[0].size  = gd->ram_size;
 172
 173        return 0;
 174}
 175
 176#ifdef CONFIG_CMD_NET
 177int board_eth_init(bd_t *bis)
 178{
 179        int rc = 0;
 180#ifdef CONFIG_SMC91111
 181        rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
 182#endif
 183        rc += pci_eth_init(bis);
 184        return rc;
 185}
 186#endif
 187