uboot/board/atmel/sama5d3xek/sama5d3xek.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2012 - 2013 Atmel Corporation
   4 * Bo Shen <voice.shen@atmel.com>
   5 */
   6
   7#include <common.h>
   8#include <init.h>
   9#include <asm/io.h>
  10#include <asm/arch/sama5d3_smc.h>
  11#include <asm/arch/at91_common.h>
  12#include <asm/arch/at91_rstc.h>
  13#include <asm/arch/gpio.h>
  14#include <asm/arch/clk.h>
  15#include <debug_uart.h>
  16#include <env.h>
  17#include <linux/ctype.h>
  18#include <spl.h>
  19#include <asm/arch/atmel_mpddrc.h>
  20#include <asm/arch/at91_wdt.h>
  21
  22DECLARE_GLOBAL_DATA_PTR;
  23
  24/* ------------------------------------------------------------------------- */
  25/*
  26 * Miscelaneous platform dependent initialisations
  27 */
  28
  29#ifdef CONFIG_NAND_ATMEL
  30void sama5d3xek_nand_hw_init(void)
  31{
  32        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  33
  34        at91_periph_clk_enable(ATMEL_ID_SMC);
  35
  36        /* Configure SMC CS3 for NAND/SmartMedia */
  37        writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  38               AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  39               &smc->cs[3].setup);
  40        writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  41               AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  42               &smc->cs[3].pulse);
  43        writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  44               &smc->cs[3].cycle);
  45        writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  46               AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
  47               AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
  48               AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  49        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  50               AT91_SMC_MODE_EXNW_DISABLE |
  51#ifdef CONFIG_SYS_NAND_DBW_16
  52               AT91_SMC_MODE_DBW_16 |
  53#else /* CONFIG_SYS_NAND_DBW_8 */
  54               AT91_SMC_MODE_DBW_8 |
  55#endif
  56               AT91_SMC_MODE_TDF_CYCLE(3),
  57               &smc->cs[3].mode);
  58}
  59#endif
  60
  61#ifdef CONFIG_MTD_NOR_FLASH
  62static void sama5d3xek_nor_hw_init(void)
  63{
  64        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  65
  66        at91_periph_clk_enable(ATMEL_ID_SMC);
  67
  68        /* Configure SMC CS0 for NOR flash */
  69        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  70               AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  71               &smc->cs[0].setup);
  72        writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
  73               AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
  74               &smc->cs[0].pulse);
  75        writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
  76               &smc->cs[0].cycle);
  77        writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0)  |
  78               AT91_SMC_TIMINGS_TAR(0)  | AT91_SMC_TIMINGS_TRR(0)   |
  79               AT91_SMC_TIMINGS_TWB(0)  | AT91_SMC_TIMINGS_RBNSEL(0)|
  80               AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
  81        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  82               AT91_SMC_MODE_EXNW_DISABLE |
  83               AT91_SMC_MODE_DBW_16 |
  84               AT91_SMC_MODE_TDF_CYCLE(1),
  85               &smc->cs[0].mode);
  86
  87        /* Address pin (A1 ~ A23) configuration */
  88        at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0);
  89        at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0);
  90        at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0);
  91        at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0);
  92        at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0);
  93        at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0);
  94        at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0);
  95        at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0);
  96        at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0);
  97        at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0);
  98        at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0);
  99        at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0);
 100        at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0);
 101        at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0);
 102        at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0);
 103        at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0);
 104        at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0);
 105        at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0);
 106        at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0);
 107        at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0);
 108        at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0);
 109        at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0);
 110        at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0);
 111        /* CS0 pin configuration */
 112        at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0);
 113}
 114#endif
 115
 116#ifdef CONFIG_CMD_USB
 117static void sama5d3xek_usb_hw_init(void)
 118{
 119        at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
 120        at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
 121        at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
 122}
 123#endif
 124
 125#ifdef CONFIG_GENERIC_ATMEL_MCI
 126static void sama5d3xek_mci_hw_init(void)
 127{
 128        at91_set_pio_output(AT91_PIO_PORTB, 10, 0);     /* MCI0 Power */
 129}
 130#endif
 131
 132#ifdef CONFIG_DEBUG_UART_BOARD_INIT
 133void board_debug_uart_init(void)
 134{
 135        at91_seriald_hw_init();
 136}
 137#endif
 138
 139#ifdef CONFIG_BOARD_EARLY_INIT_F
 140int board_early_init_f(void)
 141{
 142#ifdef CONFIG_DEBUG_UART
 143        debug_uart_init();
 144#endif
 145        return 0;
 146}
 147#endif
 148
 149int board_init(void)
 150{
 151        /* adress of boot parameters */
 152        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 153
 154#ifdef CONFIG_NAND_ATMEL
 155        sama5d3xek_nand_hw_init();
 156#endif
 157#ifdef CONFIG_MTD_NOR_FLASH
 158        sama5d3xek_nor_hw_init();
 159#endif
 160#ifdef CONFIG_CMD_USB
 161        sama5d3xek_usb_hw_init();
 162#endif
 163#ifdef CONFIG_GENERIC_ATMEL_MCI
 164        sama5d3xek_mci_hw_init();
 165#endif
 166        return 0;
 167}
 168
 169int dram_init(void)
 170{
 171        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 172                                    CONFIG_SYS_SDRAM_SIZE);
 173        return 0;
 174}
 175
 176#ifdef CONFIG_BOARD_LATE_INIT
 177int board_late_init(void)
 178{
 179#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 180        const int MAX_STR_LEN = 32;
 181        char name[MAX_STR_LEN], *p;
 182        int i;
 183
 184        strncpy(name, get_cpu_name(), MAX_STR_LEN);
 185        for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++)
 186                *p = tolower(*p);
 187
 188        strcat(name, "ek.dtb");
 189        env_set("dtb_name", name);
 190#endif
 191#ifdef CONFIG_DM_VIDEO
 192        at91_video_show_board_info();
 193#endif
 194        return 0;
 195}
 196#endif
 197
 198/* SPL */
 199#ifdef CONFIG_SPL_BUILD
 200void spl_board_init(void)
 201{
 202#if CONFIG_NAND_BOOT
 203        sama5d3xek_nand_hw_init();
 204#endif
 205}
 206
 207static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 208{
 209        ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 210
 211        ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 212                    ATMEL_MPDDRC_CR_NR_ROW_14 |
 213                    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 214                    ATMEL_MPDDRC_CR_ENRDM_ON |
 215                    ATMEL_MPDDRC_CR_NB_8BANKS |
 216                    ATMEL_MPDDRC_CR_NDQS_DISABLED |
 217                    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 218                    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 219        /*
 220         * As the DDR2-SDRAm device requires a refresh time is 7.8125us
 221         * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
 222         */
 223        ddr2->rtr = 0x411;
 224
 225        ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 226                      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 227                      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 228                      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 229                      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 230                      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 231                      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 232                      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 233
 234        ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 235                      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 236                      28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 237                      26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 238
 239        ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
 240                      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 241                      2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 242                      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 243                      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 244}
 245
 246void mem_init(void)
 247{
 248        struct atmel_mpddrc_config ddr2;
 249
 250        ddr2_conf(&ddr2);
 251
 252        /* Enable MPDDR clock */
 253        at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 254        at91_system_clk_enable(AT91_PMC_DDR);
 255
 256        /* DDRAM2 Controller initialize */
 257        ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 258}
 259
 260void at91_pmc_init(void)
 261{
 262        u32 tmp;
 263
 264        tmp = AT91_PMC_PLLAR_29 |
 265              AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 266              AT91_PMC_PLLXR_MUL(43) |
 267              AT91_PMC_PLLXR_DIV(1);
 268        at91_plla_init(tmp);
 269
 270        at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
 271
 272        tmp = AT91_PMC_MCKR_MDIV_4 |
 273              AT91_PMC_MCKR_CSS_PLLA;
 274        at91_mck_init(tmp);
 275}
 276#endif
 277