1
2
3
4
5
6
7
8
9
10#include <common.h>
11#include <cpu_func.h>
12#include <init.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/iomux-mx53.h>
16#include <asm/mach-imx/mx5_video.h>
17#include <ACEX1K.h>
18#include <asm/gpio.h>
19#include <linux/delay.h>
20
21enum LED_GPIOS {
22 GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
23 GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
24 GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
25 GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
26 GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
27 GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
28 GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
29 GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
30 GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
31 GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
32 GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
33 GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
34 GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
35 GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
36 GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
37};
38
39#define CCAT_BASE_ADDR ((void *)0xf0000000)
40#define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
41#define CCAT_SIZE 1191788
42#define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
43static const char CCAT_SIGNATURE[] = "CCAT";
44
45static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
46static const u32 CCAT_MODE_RUN = 0x0033DC8F;
47
48DECLARE_GLOBAL_DATA_PTR;
49
50u32 get_board_rev(void)
51{
52 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
53 struct fuse_bank *bank = &iim->bank[0];
54 struct fuse_bank0_regs *fuse =
55 (struct fuse_bank0_regs *)bank->fuse_regs;
56
57 int rev = readl(&fuse->gp[6]);
58
59 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
60}
61
62
63
64
65
66void weim_cs0_settings(u32 mode)
67{
68 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
69
70 writel(0x0, &weim_regs->cs0gcr1);
71 writel(mode, &weim_regs->cs0gcr1);
72 writel(0x00001002, &weim_regs->cs0gcr2);
73
74 writel(0x04000000, &weim_regs->cs0rcr1);
75 writel(0x00000000, &weim_regs->cs0rcr2);
76
77 writel(0x04000000, &weim_regs->cs0wcr1);
78 writel(0x00000000, &weim_regs->cs0wcr2);
79}
80
81static void setup_gpio_eim(void)
82{
83 gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS");
84 gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE");
85 gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG");
86 gpio_direction_input(GPIO_C3_STATUS);
87 gpio_direction_input(GPIO_C3_DONE);
88 gpio_direction_output(GPIO_C3_CONFIG, 1);
89
90 weim_cs0_settings(CCAT_MODE_RUN);
91}
92
93static void setup_gpio_sups(void)
94{
95 gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT");
96 gpio_direction_input(GPIO_SUPS_INT);
97
98 static const int BLINK_INTERVALL = 50000;
99 int status = 1;
100 while (gpio_get_value(GPIO_SUPS_INT)) {
101
102 gpio_set_value(GPIO_LED_PWR_R,
103 (++status / BLINK_INTERVALL) % 2);
104 }
105
106
107 gpio_set_value(GPIO_LED_PWR_R, 1);
108}
109
110static void setup_gpio_leds(void)
111{
112 gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R");
113 gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B");
114 gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G");
115 gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R");
116 gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B");
117 gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G");
118 gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R");
119 gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B");
120 gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G");
121
122 gpio_direction_output(GPIO_LED_SD2_R, 0);
123 gpio_direction_output(GPIO_LED_SD2_B, 0);
124 gpio_direction_output(GPIO_LED_SD2_G, 0);
125 gpio_direction_output(GPIO_LED_SD1_R, 0);
126 gpio_direction_output(GPIO_LED_SD1_B, 0);
127 gpio_direction_output(GPIO_LED_SD1_G, 0);
128 gpio_direction_output(GPIO_LED_PWR_R, 0);
129 gpio_direction_output(GPIO_LED_PWR_B, 0);
130 gpio_direction_output(GPIO_LED_PWR_G, 0);
131}
132
133static int power_init(void)
134{
135
136 return 0;
137}
138
139static void clock_1GHz(void)
140{
141 int ret;
142 u32 ref_clk = MXC_HCLK;
143
144
145
146
147 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
148 if (ret)
149 printf("CPU: Switch CPU clock to 1GHZ failed\n");
150
151 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
152 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
153 if (ret)
154 printf("CPU: Switch DDR clock to 400MHz failed\n");
155}
156
157int board_early_init_f(void)
158{
159
160 return 0;
161}
162
163int board_init(void)
164{
165 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
166
167 mxc_set_sata_internal_clock();
168
169 setup_gpio_leds();
170 setup_gpio_sups();
171 setup_gpio_eim();
172 setup_iomux_lcd();
173
174 return 0;
175}
176
177int checkboard(void)
178{
179 puts("Board: Beckhoff CX9020\n");
180
181 return 0;
182}
183
184static int ccat_config_fn(int assert_config, int flush, int cookie)
185{
186
187 weim_cs0_settings(CCAT_MODE_CONFIG);
188 gpio_set_value(GPIO_C3_CONFIG, 0);
189 udelay(1);
190 gpio_set_value(GPIO_C3_CONFIG, 1);
191 udelay(230);
192
193 return FPGA_SUCCESS;
194}
195
196static int ccat_status_fn(int cookie)
197{
198 return FPGA_FAIL;
199}
200
201static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
202{
203 const uint8_t *const buffer = buf;
204
205
206 int i;
207 for (i = 0; i < buf_len; ++i)
208 writeb(buffer[i], CCAT_BASE_ADDR);
209
210 writeb(0xff, CCAT_BASE_ADDR);
211 writeb(0xff, CCAT_BASE_ADDR);
212
213 return FPGA_SUCCESS;
214}
215
216static int ccat_done_fn(int cookie)
217{
218
219 return gpio_get_value(GPIO_C3_DONE);
220}
221
222static int ccat_post_fn(int cookie)
223{
224
225 weim_cs0_settings(CCAT_MODE_RUN);
226 invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
227
228 if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
229 printf("Verifing CCAT firmware failed, signature not found\n");
230 return FPGA_FAIL;
231 }
232
233
234 gpio_set_value(GPIO_LED_PWR_R, 1);
235 gpio_set_value(GPIO_LED_PWR_G, 1);
236 gpio_set_value(GPIO_LED_PWR_B, 0);
237 return FPGA_SUCCESS;
238}
239
240static Altera_CYC2_Passive_Serial_fns ccat_fns = {
241 .config = ccat_config_fn,
242 .status = ccat_status_fn,
243 .done = ccat_done_fn,
244 .write = ccat_write_fn,
245 .abort = ccat_post_fn,
246 .post = ccat_post_fn,
247};
248
249static Altera_desc ccat_fpga = {
250 .family = Altera_CYC2,
251 .iface = passive_serial,
252 .size = CCAT_SIZE,
253 .iface_fns = &ccat_fns,
254 .base = CCAT_BASE_ADDR,
255};
256
257int board_late_init(void)
258{
259 if (!power_init())
260 clock_1GHz();
261
262 fpga_init();
263 fpga_add(fpga_altera, &ccat_fpga);
264
265 return 0;
266}
267
