LXR uboot/board/freescale/m54418twr/m54418twr.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2010-2012 Freescale Semiconductor, Inc.
   4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   5 */
   6
   7#include <common.h>
   8#include <init.h>
   9#include <spi.h>
  10#include <asm/io.h>
  11#include <asm/immap.h>
  12#include <mmc.h>
  13#include <fsl_esdhc_imx.h>
  14#include <linux/delay.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18int checkboard(void)
  19{
  20        /*
  21         * need to to:
  22         * Check serial flash size. if 2mb evb, else 8mb demo
  23         */
  24        puts("Board: ");
  25        puts("Freescale MCF54418 Tower System\n");
  26        return 0;
  27};
  28
  29int dram_init(void)
  30{
  31        u32 dramsize;
  32
  33#if defined(CONFIG_SERIAL_BOOT)
  34        /*
  35         * Serial Boot: The dram is already initialized in start.S
  36         * only require to return DRAM size
  37         */
  38        dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
  39#else
  40        sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
  41        ccm_t *ccm = (ccm_t *)MMAP_CCM;
  42        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  43        pm_t *pm = (pm_t *) MMAP_PM;
  44        u32 i;
  45
  46        dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
  47
  48        for (i = 0x13; i < 0x20; i++) {
  49                if (dramsize == (1 << i))
  50                        break;
  51        }
  52
  53        out_8(&pm->pmcr0, 0x2E);
  54        out_8(&gpio->mscr_sdram, 1);
  55
  56        clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
  57        setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);
  58
  59        out_be32(&sdram->rcrcr, 0x40000000);
  60        out_be32(&sdram->padcr, 0x01030203);
  61
  62        out_be32(&sdram->cr00, 0x01010101);
  63        out_be32(&sdram->cr01, 0x00000101);
  64        out_be32(&sdram->cr02, 0x01010100);
  65        out_be32(&sdram->cr03, 0x01010000);
  66        out_be32(&sdram->cr04, 0x00010101);
  67        out_be32(&sdram->cr06, 0x00010100);
  68        out_be32(&sdram->cr07, 0x00000001);
  69        out_be32(&sdram->cr08, 0x01000001);
  70        out_be32(&sdram->cr09, 0x00000100);
  71        out_be32(&sdram->cr10, 0x00010001);
  72        out_be32(&sdram->cr11, 0x00000200);
  73        out_be32(&sdram->cr12, 0x01000002);
  74        out_be32(&sdram->cr13, 0x00000000);
  75        out_be32(&sdram->cr14, 0x00000100);
  76        out_be32(&sdram->cr15, 0x02000100);
  77        out_be32(&sdram->cr16, 0x02000407);
  78        out_be32(&sdram->cr17, 0x02030007);
  79        out_be32(&sdram->cr18, 0x02000100);
  80        out_be32(&sdram->cr19, 0x0A030203);
  81        out_be32(&sdram->cr20, 0x00020708);
  82        out_be32(&sdram->cr21, 0x00050008);
  83        out_be32(&sdram->cr22, 0x04030002);
  84        out_be32(&sdram->cr23, 0x00000004);
  85        out_be32(&sdram->cr24, 0x020A0000);
  86        out_be32(&sdram->cr25, 0x0C00000E);
  87        out_be32(&sdram->cr26, 0x00002004);
  88        out_be32(&sdram->cr28, 0x00100010);
  89        out_be32(&sdram->cr29, 0x00100010);
  90        out_be32(&sdram->cr31, 0x07990000);
  91        out_be32(&sdram->cr40, 0x00000000);
  92        out_be32(&sdram->cr41, 0x00C80064);
  93        out_be32(&sdram->cr42, 0x44520002);
  94        out_be32(&sdram->cr43, 0x00C80023);
  95        out_be32(&sdram->cr45, 0x0000C350);
  96        out_be32(&sdram->cr56, 0x04000000);
  97        out_be32(&sdram->cr57, 0x03000304);
  98        out_be32(&sdram->cr58, 0x40040000);
  99        out_be32(&sdram->cr59, 0xC0004004);
 100        out_be32(&sdram->cr60, 0x0642C000);
 101        out_be32(&sdram->cr61, 0x00000642);
 102        asm("tpf");
 103
 104        out_be32(&sdram->cr09, 0x01000100);
 105
 106        udelay(100);
 107#endif
 108        gd->ram_size = dramsize;
 109
 110        return 0;
 111};
 112
 113int testdram(void)
 114{
 115        return 0;
 116}
 117