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8#include <common.h>
9#include <image.h>
10#include <init.h>
11#include <net.h>
12#include <asm/io.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/imx-regs.h>
15#include <asm/arch/iomux.h>
16#include <asm/arch/mx6-pins.h>
17#include <env.h>
18#include <linux/errno.h>
19#include <asm/gpio.h>
20#include <asm/mach-imx/iomux-v3.h>
21#include <asm/mach-imx/mxc_i2c.h>
22#include <asm/mach-imx/boot_mode.h>
23#include <asm/mach-imx/spi.h>
24#include <mmc.h>
25#include <fsl_esdhc_imx.h>
26#include <miiphy.h>
27#include <asm/arch/sys_proto.h>
28#include <i2c.h>
29#include <input.h>
30#include <asm/arch/mxc_hdmi.h>
31#include <asm/mach-imx/video.h>
32#include <asm/arch/crm_regs.h>
33#include <pca953x.h>
34#include <power/pmic.h>
35#include <power/pfuze100_pmic.h>
36#include "../common/pfuze.h"
37
38DECLARE_GLOBAL_DATA_PTR;
39
40#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
41 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43
44#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
45 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
46 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
47
48#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
50
51#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
53 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
54
55#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
56#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
57 PAD_CTL_SRE_FAST)
58#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
59
60#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
61
62#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
63 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
64 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
65
66#define I2C_PMIC 1
67
68int dram_init(void)
69{
70 gd->ram_size = imx_ddr_size();
71
72 return 0;
73}
74
75static iomux_v3_cfg_t const uart4_pads[] = {
76 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
77 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
78};
79
80
81
82static struct i2c_pads_info mx6q_i2c_pad_info1 = {
83 .scl = {
84 .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
85 .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
86 .gp = IMX_GPIO_NR(2, 30)
87 },
88 .sda = {
89 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
90 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
91 .gp = IMX_GPIO_NR(4, 13)
92 }
93};
94
95static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
96 .scl = {
97 .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
98 .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
99 .gp = IMX_GPIO_NR(2, 30)
100 },
101 .sda = {
102 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
103 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
104 .gp = IMX_GPIO_NR(4, 13)
105 }
106};
107
108#ifndef CONFIG_SYS_FLASH_CFI
109
110
111
112
113static struct i2c_pads_info mx6q_i2c_pad_info2 = {
114 .scl = {
115 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
116 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
117 .gp = IMX_GPIO_NR(1, 3)
118 },
119 .sda = {
120 .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
121 .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
122 .gp = IMX_GPIO_NR(3, 18)
123 }
124};
125
126static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
127 .scl = {
128 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
129 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
130 .gp = IMX_GPIO_NR(1, 3)
131 },
132 .sda = {
133 .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
134 .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
135 .gp = IMX_GPIO_NR(3, 18)
136 }
137};
138#endif
139
140static iomux_v3_cfg_t const i2c3_pads[] = {
141 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
142};
143
144static iomux_v3_cfg_t const port_exp[] = {
145 IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
146};
147
148#ifdef CONFIG_MTD_NOR_FLASH
149static iomux_v3_cfg_t const eimnor_pads[] = {
150 IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
151 IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
152 IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
153 IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
154 IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
155 IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
156 IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
157 IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
158 IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
159 IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
160 IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
161 IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
162 IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
163 IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
164 IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
165 IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
166 IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
167 IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
168 IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
169 IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
170 IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
171 IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
172 IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
173 IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
174 IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
175 IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
176 IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
177 IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
178 IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
179 IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
180 IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
181 IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
182 IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
183 IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
184 IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
185 IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
186 IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
187 IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
188 IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
189 IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
190 IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
191 IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
192 IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
193};
194
195static void eimnor_cs_setup(void)
196{
197 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
198
199 writel(0x00020181, &weim_regs->cs0gcr1);
200 writel(0x00000001, &weim_regs->cs0gcr2);
201 writel(0x0a020000, &weim_regs->cs0rcr1);
202 writel(0x0000c000, &weim_regs->cs0rcr2);
203 writel(0x0804a240, &weim_regs->cs0wcr1);
204 writel(0x00000120, &weim_regs->wcr);
205
206 set_chipselect_size(CS0_128);
207}
208
209static void eim_clk_setup(void)
210{
211 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
212 int cscmr1, ccgr6;
213
214
215
216 ccgr6 = readl(&imx_ccm->CCGR6);
217 ccgr6 &= ~(0x3 << 10);
218 writel(ccgr6, &imx_ccm->CCGR6);
219
220
221
222
223
224
225 cscmr1 = readl(&imx_ccm->cscmr1);
226 cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
227 MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
228 cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
229 writel(cscmr1, &imx_ccm->cscmr1);
230
231
232 ccgr6 |= (0x3 << 10);
233 writel(ccgr6, &imx_ccm->CCGR6);
234}
235
236static void setup_iomux_eimnor(void)
237{
238 SETUP_IOMUX_PADS(eimnor_pads);
239
240 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
241
242 eimnor_cs_setup();
243}
244#endif
245
246
247static iomux_v3_cfg_t const usdhc3_pads[] = {
248 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
249 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
250 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
251 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
252 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
253 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
254 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
255 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
256 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
257 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
258 IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
259 IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
260};
261
262static void setup_iomux_uart(void)
263{
264 SETUP_IOMUX_PADS(uart4_pads);
265}
266
267#ifdef CONFIG_FSL_ESDHC_IMX
268static struct fsl_esdhc_cfg usdhc_cfg[1] = {
269 {USDHC3_BASE_ADDR},
270};
271
272int board_mmc_getcd(struct mmc *mmc)
273{
274 gpio_direction_input(IMX_GPIO_NR(6, 15));
275 return !gpio_get_value(IMX_GPIO_NR(6, 15));
276}
277
278int board_mmc_init(bd_t *bis)
279{
280 SETUP_IOMUX_PADS(usdhc3_pads);
281
282 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
283 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
284}
285#endif
286
287#ifdef CONFIG_NAND_MXS
288static iomux_v3_cfg_t gpmi_pads[] = {
289 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
290 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
291 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
292 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
293 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
294 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
295 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
296 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
297 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
298 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
299 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
300 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
301 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
302 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
303 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
304 IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
305};
306
307static void setup_gpmi_nand(void)
308{
309 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
310
311
312 SETUP_IOMUX_PADS(gpmi_pads);
313
314 setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
315 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
316 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
317
318
319 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
320}
321#endif
322
323u32 get_board_rev(void)
324{
325 int rev = nxp_board_rev();
326
327 return (get_cpu_rev() & ~(0xF << 8)) | rev;
328}
329
330static int ar8031_phy_fixup(struct phy_device *phydev)
331{
332 unsigned short val;
333
334
335 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
336 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
337 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
338
339 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
340 val &= 0xffe3;
341 val |= 0x18;
342 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
343
344
345 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
346 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
347 val |= 0x0100;
348 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
349
350 return 0;
351}
352
353int board_phy_config(struct phy_device *phydev)
354{
355 ar8031_phy_fixup(phydev);
356
357 if (phydev->drv->config)
358 phydev->drv->config(phydev);
359
360 return 0;
361}
362
363#if defined(CONFIG_VIDEO_IPUV3)
364static void disable_lvds(struct display_info_t const *dev)
365{
366 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
367
368 clrbits_le32(&iomux->gpr[2],
369 IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
370 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
371}
372
373static void do_enable_hdmi(struct display_info_t const *dev)
374{
375 disable_lvds(dev);
376 imx_enable_hdmi_phy();
377}
378
379struct display_info_t const displays[] = {{
380 .bus = -1,
381 .addr = 0,
382 .pixfmt = IPU_PIX_FMT_RGB666,
383 .detect = NULL,
384 .enable = NULL,
385 .mode = {
386 .name = "Hannstar-XGA",
387 .refresh = 60,
388 .xres = 1024,
389 .yres = 768,
390 .pixclock = 15385,
391 .left_margin = 220,
392 .right_margin = 40,
393 .upper_margin = 21,
394 .lower_margin = 7,
395 .hsync_len = 60,
396 .vsync_len = 10,
397 .sync = FB_SYNC_EXT,
398 .vmode = FB_VMODE_NONINTERLACED
399} }, {
400 .bus = -1,
401 .addr = 0,
402 .pixfmt = IPU_PIX_FMT_RGB24,
403 .detect = detect_hdmi,
404 .enable = do_enable_hdmi,
405 .mode = {
406 .name = "HDMI",
407 .refresh = 60,
408 .xres = 1024,
409 .yres = 768,
410 .pixclock = 15385,
411 .left_margin = 220,
412 .right_margin = 40,
413 .upper_margin = 21,
414 .lower_margin = 7,
415 .hsync_len = 60,
416 .vsync_len = 10,
417 .sync = FB_SYNC_EXT,
418 .vmode = FB_VMODE_NONINTERLACED,
419} } };
420size_t display_count = ARRAY_SIZE(displays);
421
422iomux_v3_cfg_t const backlight_pads[] = {
423 IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
424};
425
426static void setup_iomux_backlight(void)
427{
428 gpio_request(IMX_GPIO_NR(2, 9), "backlight");
429 gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
430 SETUP_IOMUX_PADS(backlight_pads);
431}
432
433static void setup_display(void)
434{
435 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
436 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
437 int reg;
438
439 setup_iomux_backlight();
440 enable_ipu_clock();
441 imx_setup_hdmi();
442
443
444 reg = readl(&mxc_ccm->CCGR3);
445 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
446 writel(reg, &mxc_ccm->CCGR3);
447
448
449 reg = readl(&mxc_ccm->cs2cdr);
450 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
451 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
452 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
453 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
454 writel(reg, &mxc_ccm->cs2cdr);
455
456 reg = readl(&mxc_ccm->cscmr2);
457 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
458 writel(reg, &mxc_ccm->cscmr2);
459
460 reg = readl(&mxc_ccm->chsccdr);
461 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
462 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
463 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
464 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
465 writel(reg, &mxc_ccm->chsccdr);
466
467 reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
468 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
469 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
470 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
471 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
472 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
473 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
474 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
475 writel(reg, &iomux->gpr[2]);
476
477 reg = readl(&iomux->gpr[3]);
478 reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
479 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
480 reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
481 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
482 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
483 IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
484 writel(reg, &iomux->gpr[3]);
485}
486#endif
487
488
489
490
491
492int overwrite_console(void)
493{
494 return 1;
495}
496
497int board_early_init_f(void)
498{
499 setup_iomux_uart();
500
501#ifdef CONFIG_NAND_MXS
502 setup_gpmi_nand();
503#endif
504
505#ifdef CONFIG_MTD_NOR_FLASH
506 eim_clk_setup();
507#endif
508 return 0;
509}
510
511int board_init(void)
512{
513
514 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
515
516
517 if (is_mx6dq() || is_mx6dqp())
518 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
519 else
520 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
521
522 gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
523 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
524 SETUP_IOMUX_PADS(i2c3_pads);
525#ifndef CONFIG_SYS_FLASH_CFI
526 if (is_mx6dq() || is_mx6dqp())
527 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
528 else
529 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
530#endif
531 gpio_request(IMX_GPIO_NR(1, 15), "expander en");
532 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
533 SETUP_IOMUX_PADS(port_exp);
534
535#ifdef CONFIG_VIDEO_IPUV3
536 setup_display();
537#endif
538
539#ifdef CONFIG_MTD_NOR_FLASH
540 setup_iomux_eimnor();
541#endif
542 return 0;
543}
544
545#ifdef CONFIG_MXC_SPI
546int board_spi_cs_gpio(unsigned bus, unsigned cs)
547{
548 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
549}
550#endif
551
552int power_init_board(void)
553{
554 struct pmic *p;
555 unsigned int value;
556
557 p = pfuze_common_init(I2C_PMIC);
558 if (!p)
559 return -ENODEV;
560
561 if (is_mx6dqp()) {
562
563 pmic_reg_read(p, PFUZE100_SW2STBY, &value);
564 value &= ~0x3f;
565 value |= 0x17;
566 pmic_reg_write(p, PFUZE100_SW2STBY, value);
567 }
568
569 return pfuze_mode_init(p, APS_PFM);
570}
571
572#ifdef CONFIG_CMD_BMODE
573static const struct boot_mode board_boot_modes[] = {
574
575 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
576 {NULL, 0},
577};
578#endif
579
580int board_late_init(void)
581{
582#ifdef CONFIG_CMD_BMODE
583 add_board_boot_modes(board_boot_modes);
584#endif
585
586#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
587 env_set("board_name", "SABREAUTO");
588
589 if (is_mx6dqp())
590 env_set("board_rev", "MX6QP");
591 else if (is_mx6dq())
592 env_set("board_rev", "MX6Q");
593 else if (is_mx6sdl())
594 env_set("board_rev", "MX6DL");
595#endif
596
597 return 0;
598}
599
600int checkboard(void)
601{
602 printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
603
604 return 0;
605}
606
607#ifdef CONFIG_USB_EHCI_MX6
608int board_ehci_hcd_init(int port)
609{
610 switch (port) {
611 case 0:
612
613
614
615
616 imx_iomux_set_gpr_register(1, 13, 1, 0);
617 break;
618 case 1:
619 break;
620 default:
621 printf("MXC USB port %d not yet supported\n", port);
622 return -EINVAL;
623 }
624 return 0;
625}
626#endif
627
628#ifdef CONFIG_SPL_BUILD
629#include <asm/arch/mx6-ddr.h>
630#include <spl.h>
631#include <linux/libfdt.h>
632
633#ifdef CONFIG_SPL_OS_BOOT
634int spl_start_uboot(void)
635{
636 return 0;
637}
638#endif
639
640static void ccgr_init(void)
641{
642 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
643
644 writel(0x00C03F3F, &ccm->CCGR0);
645 writel(0x0030FC03, &ccm->CCGR1);
646 writel(0x0FFFC000, &ccm->CCGR2);
647 writel(0x3FF00000, &ccm->CCGR3);
648 writel(0x00FFF300, &ccm->CCGR4);
649 writel(0x0F0000C3, &ccm->CCGR5);
650 writel(0x000003FF, &ccm->CCGR6);
651}
652
653static int mx6q_dcd_table[] = {
654 0x020e0798, 0x000C0000,
655 0x020e0758, 0x00000000,
656 0x020e0588, 0x00000030,
657 0x020e0594, 0x00000030,
658 0x020e056c, 0x00000030,
659 0x020e0578, 0x00000030,
660 0x020e074c, 0x00000030,
661 0x020e057c, 0x00000030,
662 0x020e058c, 0x00000000,
663 0x020e059c, 0x00000030,
664 0x020e05a0, 0x00000030,
665 0x020e078c, 0x00000030,
666 0x020e0750, 0x00020000,
667 0x020e05a8, 0x00000028,
668 0x020e05b0, 0x00000028,
669 0x020e0524, 0x00000028,
670 0x020e051c, 0x00000028,
671 0x020e0518, 0x00000028,
672 0x020e050c, 0x00000028,
673 0x020e05b8, 0x00000028,
674 0x020e05c0, 0x00000028,
675 0x020e0774, 0x00020000,
676 0x020e0784, 0x00000028,
677 0x020e0788, 0x00000028,
678 0x020e0794, 0x00000028,
679 0x020e079c, 0x00000028,
680 0x020e07a0, 0x00000028,
681 0x020e07a4, 0x00000028,
682 0x020e07a8, 0x00000028,
683 0x020e0748, 0x00000028,
684 0x020e05ac, 0x00000028,
685 0x020e05b4, 0x00000028,
686 0x020e0528, 0x00000028,
687 0x020e0520, 0x00000028,
688 0x020e0514, 0x00000028,
689 0x020e0510, 0x00000028,
690 0x020e05bc, 0x00000028,
691 0x020e05c4, 0x00000028,
692 0x021b0800, 0xa1390003,
693 0x021b080c, 0x001F001F,
694 0x021b0810, 0x001F001F,
695 0x021b480c, 0x001F001F,
696 0x021b4810, 0x001F001F,
697 0x021b083c, 0x43260335,
698 0x021b0840, 0x031A030B,
699 0x021b483c, 0x4323033B,
700 0x021b4840, 0x0323026F,
701 0x021b0848, 0x483D4545,
702 0x021b4848, 0x44433E48,
703 0x021b0850, 0x41444840,
704 0x021b4850, 0x4835483E,
705 0x021b081c, 0x33333333,
706 0x021b0820, 0x33333333,
707 0x021b0824, 0x33333333,
708 0x021b0828, 0x33333333,
709 0x021b481c, 0x33333333,
710 0x021b4820, 0x33333333,
711 0x021b4824, 0x33333333,
712 0x021b4828, 0x33333333,
713 0x021b08b8, 0x00000800,
714 0x021b48b8, 0x00000800,
715 0x021b0004, 0x00020036,
716 0x021b0008, 0x09444040,
717 0x021b000c, 0x8A8F7955,
718 0x021b0010, 0xFF328F64,
719 0x021b0014, 0x01FF00DB,
720 0x021b0018, 0x00001740,
721 0x021b001c, 0x00008000,
722 0x021b002c, 0x000026d2,
723 0x021b0030, 0x008F1023,
724 0x021b0040, 0x00000047,
725 0x021b0000, 0x841A0000,
726 0x021b001c, 0x04088032,
727 0x021b001c, 0x00008033,
728 0x021b001c, 0x00048031,
729 0x021b001c, 0x09408030,
730 0x021b001c, 0x04008040,
731 0x021b0020, 0x00005800,
732 0x021b0818, 0x00011117,
733 0x021b4818, 0x00011117,
734 0x021b0004, 0x00025576,
735 0x021b0404, 0x00011006,
736 0x021b001c, 0x00000000,
737 0x020c4068, 0x00C03F3F,
738 0x020c406c, 0x0030FC03,
739 0x020c4070, 0x0FFFC000,
740 0x020c4074, 0x3FF00000,
741 0x020c4078, 0xFFFFF300,
742 0x020c407c, 0x0F0000F3,
743 0x020c4080, 0x00000FFF,
744 0x020e0010, 0xF00000CF,
745 0x020e0018, 0x007F007F,
746 0x020e001c, 0x007F007F,
747};
748
749static int mx6qp_dcd_table[] = {
750 0x020e0798, 0x000C0000,
751 0x020e0758, 0x00000000,
752 0x020e0588, 0x00000030,
753 0x020e0594, 0x00000030,
754 0x020e056c, 0x00000030,
755 0x020e0578, 0x00000030,
756 0x020e074c, 0x00000030,
757 0x020e057c, 0x00000030,
758 0x020e058c, 0x00000000,
759 0x020e059c, 0x00000030,
760 0x020e05a0, 0x00000030,
761 0x020e078c, 0x00000030,
762 0x020e0750, 0x00020000,
763 0x020e05a8, 0x00000030,
764 0x020e05b0, 0x00000030,
765 0x020e0524, 0x00000030,
766 0x020e051c, 0x00000030,
767 0x020e0518, 0x00000030,
768 0x020e050c, 0x00000030,
769 0x020e05b8, 0x00000030,
770 0x020e05c0, 0x00000030,
771 0x020e0774, 0x00020000,
772 0x020e0784, 0x00000030,
773 0x020e0788, 0x00000030,
774 0x020e0794, 0x00000030,
775 0x020e079c, 0x00000030,
776 0x020e07a0, 0x00000030,
777 0x020e07a4, 0x00000030,
778 0x020e07a8, 0x00000030,
779 0x020e0748, 0x00000030,
780 0x020e05ac, 0x00000030,
781 0x020e05b4, 0x00000030,
782 0x020e0528, 0x00000030,
783 0x020e0520, 0x00000030,
784 0x020e0514, 0x00000030,
785 0x020e0510, 0x00000030,
786 0x020e05bc, 0x00000030,
787 0x020e05c4, 0x00000030,
788 0x021b0800, 0xa1390003,
789 0x021b080c, 0x001b001e,
790 0x021b0810, 0x002e0029,
791 0x021b480c, 0x001b002a,
792 0x021b4810, 0x0019002c,
793 0x021b083c, 0x43240334,
794 0x021b0840, 0x0324031a,
795 0x021b483c, 0x43340344,
796 0x021b4840, 0x03280276,
797 0x021b0848, 0x44383A3E,
798 0x021b4848, 0x3C3C3846,
799 0x021b0850, 0x2e303230,
800 0x021b4850, 0x38283E34,
801 0x021b081c, 0x33333333,
802 0x021b0820, 0x33333333,
803 0x021b0824, 0x33333333,
804 0x021b0828, 0x33333333,
805 0x021b481c, 0x33333333,
806 0x021b4820, 0x33333333,
807 0x021b4824, 0x33333333,
808 0x021b4828, 0x33333333,
809 0x021b08c0, 0x24912492,
810 0x021b48c0, 0x24912492,
811 0x021b08b8, 0x00000800,
812 0x021b48b8, 0x00000800,
813 0x021b0004, 0x00020036,
814 0x021b0008, 0x09444040,
815 0x021b000c, 0x898E7955,
816 0x021b0010, 0xFF328F64,
817 0x021b0014, 0x01FF00DB,
818 0x021b0018, 0x00001740,
819 0x021b001c, 0x00008000,
820 0x021b002c, 0x000026d2,
821 0x021b0030, 0x008E1023,
822 0x021b0040, 0x00000047,
823 0x021b0400, 0x14420000,
824 0x021b0000, 0x841A0000,
825 0x00bb0008, 0x00000004,
826 0x00bb000c, 0x2891E41A,
827 0x00bb0038, 0x00000564,
828 0x00bb0014, 0x00000040,
829 0x00bb0028, 0x00000020,
830 0x00bb002c, 0x00000020,
831 0x021b001c, 0x04088032,
832 0x021b001c, 0x00008033,
833 0x021b001c, 0x00048031,
834 0x021b001c, 0x09408030,
835 0x021b001c, 0x04008040,
836 0x021b0020, 0x00005800,
837 0x021b0818, 0x00011117,
838 0x021b4818, 0x00011117,
839 0x021b0004, 0x00025576,
840 0x021b0404, 0x00011006,
841 0x021b001c, 0x00000000,
842 0x020c4068, 0x00C03F3F,
843 0x020c406c, 0x0030FC03,
844 0x020c4070, 0x0FFFC000,
845 0x020c4074, 0x3FF00000,
846 0x020c4078, 0xFFFFF300,
847 0x020c407c, 0x0F0000F3,
848 0x020c4080, 0x00000FFF,
849 0x020e0010, 0xF00000CF,
850 0x020e0018, 0x77177717,
851 0x020e001c, 0x77177717,
852};
853
854static int mx6dl_dcd_table[] = {
855 0x020e0774, 0x000C0000,
856 0x020e0754, 0x00000000,
857 0x020e04ac, 0x00000030,
858 0x020e04b0, 0x00000030,
859 0x020e0464, 0x00000030,
860 0x020e0490, 0x00000030,
861 0x020e074c, 0x00000030,
862 0x020e0494, 0x00000030,
863 0x020e04a0, 0x00000000,
864 0x020e04b4, 0x00000030,
865 0x020e04b8, 0x00000030,
866 0x020e076c, 0x00000030,
867 0x020e0750, 0x00020000,
868 0x020e04bc, 0x00000028,
869 0x020e04c0, 0x00000028,
870 0x020e04c4, 0x00000028,
871 0x020e04c8, 0x00000028,
872 0x020e04cc, 0x00000028,
873 0x020e04d0, 0x00000028,
874 0x020e04d4, 0x00000028,
875 0x020e04d8, 0x00000028,
876 0x020e0760, 0x00020000,
877 0x020e0764, 0x00000028,
878 0x020e0770, 0x00000028,
879 0x020e0778, 0x00000028,
880 0x020e077c, 0x00000028,
881 0x020e0780, 0x00000028,
882 0x020e0784, 0x00000028,
883 0x020e078c, 0x00000028,
884 0x020e0748, 0x00000028,
885 0x020e0470, 0x00000028,
886 0x020e0474, 0x00000028,
887 0x020e0478, 0x00000028,
888 0x020e047c, 0x00000028,
889 0x020e0480, 0x00000028,
890 0x020e0484, 0x00000028,
891 0x020e0488, 0x00000028,
892 0x020e048c, 0x00000028,
893 0x021b0800, 0xa1390003,
894 0x021b080c, 0x001F001F,
895 0x021b0810, 0x001F001F,
896 0x021b480c, 0x001F001F,
897 0x021b4810, 0x001F001F,
898 0x021b083c, 0x42190217,
899 0x021b0840, 0x017B017B,
900 0x021b483c, 0x4176017B,
901 0x021b4840, 0x015F016C,
902 0x021b0848, 0x4C4C4D4C,
903 0x021b4848, 0x4A4D4C48,
904 0x021b0850, 0x3F3F3F40,
905 0x021b4850, 0x3538382E,
906 0x021b081c, 0x33333333,
907 0x021b0820, 0x33333333,
908 0x021b0824, 0x33333333,
909 0x021b0828, 0x33333333,
910 0x021b481c, 0x33333333,
911 0x021b4820, 0x33333333,
912 0x021b4824, 0x33333333,
913 0x021b4828, 0x33333333,
914 0x021b08b8, 0x00000800,
915 0x021b48b8, 0x00000800,
916 0x021b0004, 0x00020025,
917 0x021b0008, 0x00333030,
918 0x021b000c, 0x676B5313,
919 0x021b0010, 0xB66E8B63,
920 0x021b0014, 0x01FF00DB,
921 0x021b0018, 0x00001740,
922 0x021b001c, 0x00008000,
923 0x021b002c, 0x000026d2,
924 0x021b0030, 0x006B1023,
925 0x021b0040, 0x00000047,
926 0x021b0000, 0x841A0000,
927 0x021b001c, 0x04008032,
928 0x021b001c, 0x00008033,
929 0x021b001c, 0x00048031,
930 0x021b001c, 0x05208030,
931 0x021b001c, 0x04008040,
932 0x021b0020, 0x00005800,
933 0x021b0818, 0x00011117,
934 0x021b4818, 0x00011117,
935 0x021b0004, 0x00025565,
936 0x021b0404, 0x00011006,
937 0x021b001c, 0x00000000,
938 0x020c4068, 0x00C03F3F,
939 0x020c406c, 0x0030FC03,
940 0x020c4070, 0x0FFFC000,
941 0x020c4074, 0x3FF00000,
942 0x020c4078, 0xFFFFF300,
943 0x020c407c, 0x0F0000C3,
944 0x020c4080, 0x00000FFF,
945 0x020e0010, 0xF00000CF,
946 0x020e0018, 0x007F007F,
947 0x020e001c, 0x007F007F,
948};
949
950static void ddr_init(int *table, int size)
951{
952 int i;
953
954 for (i = 0; i < size / 2 ; i++)
955 writel(table[2 * i + 1], table[2 * i]);
956}
957
958static void spl_dram_init(void)
959{
960 if (is_mx6dq())
961 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
962 else if (is_mx6dqp())
963 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
964 else if (is_mx6sdl())
965 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
966}
967
968void board_init_f(ulong dummy)
969{
970
971 spl_dram_init();
972
973
974 arch_cpu_init();
975
976 ccgr_init();
977 gpr_init();
978
979
980 board_early_init_f();
981
982
983 timer_init();
984
985
986 preloader_console_init();
987
988
989 memset(__bss_start, 0, __bss_end - __bss_start);
990
991
992 board_init_r(NULL, 0);
993}
994#endif
995
996#ifdef CONFIG_SPL_LOAD_FIT
997int board_fit_config_name_match(const char *name)
998{
999 if (is_mx6dq()) {
1000 if (!strcmp(name, "imx6q-sabreauto"))
1001 return 0;
1002 } else if (is_mx6dqp()) {
1003 if (!strcmp(name, "imx6qp-sabreauto"))
1004 return 0;
1005 } else if (is_mx6dl()) {
1006 if (!strcmp(name, "imx6dl-sabreauto"))
1007 return 0;
1008 }
1009
1010 return -1;
1011}
1012#endif
1013
